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Title:
CAPACITANCE-BASED MULTI-LAYER SYNAPSE DEVICE AND MANUFACTURING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2019/093724
Kind Code:
A1
Abstract:
The present invention provides a capacitance-based multi-layer synapse device and a manufacturing method therefor, the device comprising: a unit horizontal stacked structure in which horizontal conductive lines extending in a first direction and horizontal insulation layers for providing insulation between the horizontal conductive lines are alternately stacked in a third direction; a unit vertical array structure in which vertical conductive lines extending in the third direction and vertical insulation layers for providing insulation between the vertical conductive lines are alternately stacked in the first direction; a cross-point structure interposed between the unit horizontal stacked structure and the unit vertical array structure and having a resistance-switching layer repeatedly stacked in a second direction; a capacitor structure formed on the cross-point structure, and comprising a plurality of capacitors electrically connected to the vertical conductive lines; and a conductive plate formed on the capacitor structure, and adding up charges accumulated in the capacitor structure, wherein cross point nodes defined by regions, in which the horizontal conductive lines and the vertical conductive lines intersect, in the resistance-switching layer form or do not form a conductive path according to a weighted value provided to the horizontal conductive lines.

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Inventors:
YOO IN KYEONG (KR)
HWANG HYUNSANG (KR)
Application Number:
PCT/KR2018/013297
Publication Date:
May 16, 2019
Filing Date:
November 05, 2018
Export Citation:
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Assignee:
POSTECH ACAD IND FOUND (KR)
International Classes:
G06N3/063; H01L49/02
Foreign References:
KR20170098673A2017-08-30
US20170033120A12017-02-02
KR20170108627A2017-09-27
KR20170117863A2017-10-24
KR20150034900A2015-04-06
Attorney, Agent or Firm:
JANG, In Seok (KR)
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