[0001] This application is being filed on July 14, 2015, as a PCT International Patent application and claims priority to U.S. Patent Application Serial No. 62/024,754 filed on 5 July 15, 2014, the disclosure of which is incorporated herein by reference in its entirety. Background

[0002] The present disclosure relates generally to electrical connectors. [0003] Electrical connectors that are commonly used in telecommunication systems provide an interface between successive runs of cables and/or between cables and 10 electronic devices of the system. Some of such electrical connectors, for example modular jacks, are configured to be joined with a mating plug having an array of mating contacts. A printed circuit may be provided to establish an electrical connection between the mating contacts and the cable or electronic device. [0004] . The performance of some electrical connectors, such as modular jacks and plugs, 15 may be negatively affected by crosstalk generated along the signal path between adjacent differential pairs of the mating contacts of the electrical connector. To improve the performance of the connectors, techniques are used to provide compensation for the crosstalk. For example, some known techniques arrange the contacts and/or conductive traces of the printed circuit with respect to each other provide the compensation. 20 [0005] Improvements in crosstalk compensation are desired. Summary

[0006] In accordance with aspects of the present disclosure a capacitive coupling system includes a plurality of conductive pads situated on a dielectric layer. A plurality of switches are connected between pairs of the conductive pads via conductive linkages. 25 The switches are operable to selectively connect selected pairs of the conductive pads.

The capacitive coupling system is used in conjunction with an electrical connector in some embodiments. The electrical connector includes a plurality of conductive traces situated on a substrate that are arranged as differential pairs. One side of the dielectric is positioned adjacent the conductive traces, and the conductive pads are situated on the opposite side of the dielectric layer. The switches selectively connect selected pairs of the conductive pads to adjust capacitive coupling between the differential pairs of the conductive traces. Brief Description of the Drawings

5 [0007] Figure 1 is a perspective view illustrating aspects of an electrical connector system in accordance with aspects of the present disclosure. [0008] Figure 2 is a block diagram conceptually illustrating capacitive coupling between conductor pairs of an electrical connector for crosstalk compensation. [0009] Figure 3 is a schematic diagram illustrating a Wheatstone bridge circuit formed by 10 the coupling capacitances shown in Figure 2. [0010] Figure 4 is a schematic diagram illustrating the Wheatstone bridge circuit of Figure 3, further including additional capacitances to balance the bridge. [0011] Figures 5A, 5B and 5C are end views illustrating examples of conductive traces of an electrical connector situated on a substrate, where Figure 5A illustrates ideal trace15 structure, Figure 5B illustrates an over-etch condition and Figure 5C illustrates and under- etch condition. [0012] Figure 6 is a block diagram illustrating an example of a crosstalk compensation system in accordance with aspects of the present disclosure. [0013] Figure 7 is a schematic top view illustrating portions of an application specific 20 integrated circuit (ASIC) of the crosstalk compensation system shown in Figure 6. [0014] Figures 8A and 8B are end views of the ASIC shown in Figure 7, [0015] Figure 9 is a block diagram illustrating examples of layers included in the ASIC shown in Figures 7 and 8. [0016] Figure 10 is a flow diagram illustrating an example of a capacitive compensation 25 system in accordance with aspects of the present disclosure. Detailed Description

[0017] In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional 5 terminology, such as top, bottom, front, back, etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope 10 of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense. [0018] Some electrical connectors, such as modular jacks, may be negatively affected by crosstalk generated along the signal path between adjacent differential pairs of the mating contacts of the electrical connector. In accordance with certain aspects of the present 15 disclosure, finite capacitive coupling across signal conductor paths is provided to mitigate the imbalance created by manufacturing tolerances and physical displacement of conducting paths. The disclosed capacitive coupling could be provided, for example, in connector assemblies using printed circuit boards (PCBs) to provide electrical connections within the connector, or in other types of interconnects such as lead frames. 20 [0019] Figure 1 is perspective view illustrating an example of an electrical connector 100.

The connector 100 shown in Figure 1 is a modular connector, such as, but not limited to, an RJ-45 outlet or communication jack. However, the subject matter described and/or illustrated herein is applicable to other types of electrical connectors. The connector 100 is configured to receive and engage a mating plug, such as a modular plug (also referred to 25 as a mating connector). The modular plug is loaded along a mating direction, shown generally by arrow A. The connector 100 includes a connector body 101 having a mating end 104 that is configured to receive and engage the modular plug and a loading end 106 that is configured to electrically and mechanically engage a cable 126. The connector body 101 may include a housing 102 extending from the mating end 104 and toward the loading 30 end 106. The housing 102 may at least partially define an interior chamber 108 that

extends therebetween and is configured to receive the modular plug proximate the mating end 104. Attorney Docket No. 02316.3964WOU1 [0020] The connector 100 includes an array 117 of mating conductors or contacts 118. Each mating conductor 118 within the array 117 includes a mating interface 120 arranged within the chamber 108. Each mating interface 120 engages (i.e., interfaces with) a corresponding mating or plug contact of the modular plug when the modular plug is mated 5 with the connector 100. The arrangement of the mating conductors 118 may be at least partially determined by industry standards, such as, but not limited to, International Electrotechnical Commission (IEC) 60603-7 or Electronics Industries

Alliance/Telecommunications Industry Association (EIA/TIA)-568. In some examples, the connector 100 includes eight mating conductors 118 arranged as differential pairs.

10 However, the connector 100 may include any number of mating conductors 118, whether or not the mating conductors 118 are arranged in differential pairs. [0021] Some PCBs used for connector applications such as the connector 100 have conductive traces that are laid out in such a way to cause signal coupling between different conductive traces. This coupling is designed to balance out the capacitive imbalance 15 created by manufacturing tolerances and physical placement of the other conductive

traces. Figure 2 illustrates an example of such coupling between eight conductors 150 of the connector 100. For simplicity, only the 4,5 and 3,6 differential pair combinations of a PCB mounted RJ45 will be discussed. As conceptually illustrated in Figure 2, the conductors 150 are situated such that capacitors 152 are formed therebetween. 20 [0022] The assumption is that the magnitude of the capacitive coupling between two

adjacent pins is the unit value C. Since these are differential pairs, the coupling between the non-adjacent pins must also be considered. In this example, the distance between 3-5 and 4-6 is twice that of 3-4 and 5-6 therefore the magnitude of coupling capacitance is C/2. 25 [0023] Capacitance between any two conductors is inversely proportion to the distance between them as given by the following equation:

[0025] Where H _r is the permittivity of the dielectric material (e.g., air, polyimide, Teflon, etc.), is the permittivity of a vacuum

4 universal constant), A is the surface area of the plates, and d is the distance between the plates. Any two metallic surfaces can form a coupling or parasitic capacitance provided they are galvanically isolated and have some form of dielectric media between them. For example, two metal plates suspended with air between them, two metals plates rolled or 5 stacked together with a dielectric media between them, pins on a connector (or IC) with air or some dielectric media between them, or traces on a PCB separated by air or a dielectric media (e.g., solder mask material or conformal coating). In addition, points of concentricity (e.g., edge of a conductor) can contribute to the coupling by what is referred to as the“edge effect”. The contribution the magnitude of the capacitance by this effect is 10 random and unpredictable. It is also a major contributor to cross-talk and is very

susceptible to process control in PCB manufacturing. [0026] Figure 3 schematically illustrates a Wheatstone bridge 160 formed by the coupling capacitances. The signal source v _s (t) is the disturbing voltage (or signal) and v _n (t) is the noise or crosstalk voltage produced by the imbalance of the bridge. If C is unit

15 capacitance (unity), then C/2 is ½. This allows the magnitude of the noise voltage to be verified mathematically as follows:

[0029] The magnitude of the noise voltage is 1/3 of the magnitude of the input voltage. 20 For the noise voltage to be zero, the bridge 160 must be balanced by the addition of

capacitance 162 as shown in Figure 4. [0030] Connecting capacitors in parallel results in a value that is the sum of the two capacitances. Adding a capacitance 164 of C/2 to the 4,6, and 3,5 conductive pairs results in the following value. 25 [0031]

[0032] If C is unit capacitance (unity), the balanced to be verified mathematically as follows: _[0033]

[0034]

[0035] The most common technique used to mitigate (e.g., tune) the noise or cross-talk voltage involves the positioning of PCB traces to increase the capacitive coupling between 5 the non-adjacent pairs. This is quite effective assuming that the position of the connector contacts is always consistent and the PCBs used for interconnection are always manufactured using processes that produce consistent PCBs. [0036] PCBs that have been tuned to remove imbalances for cross-talk performance requires must be manufacturing consistently. Figures 5A, 5B and 5C conceptually 10 illustrate aspects of different conductive traces 170 situated on a PCB substrate 172. The PCB cross section shown in Figure 5A what an ideal trace structure would look like. The cross section shown in Figure 5B is an over-etch condition and the cross section in Figure 5C is an under-etch condition. In Figure 5A, C is the unit capacitance between two adjacent traces 170 and C _f is the fringe capacitance. 15 [0037] PCBs used in an RJ45 application, for example, may require a considerable

amount of tuning to mitigate the cross-talk effect caused by an imbalanced arrangement of connector contacts. In addition, the capacitive coupling is usually in the pico and femto farad range (10 ^-12 – 10 ^-15 ), which makes the tuning susceptible to variations in PCB fabrication. 20 [0038] Another method is to locate a mid-point and reverse one conductive pair. This reverses the phase of part of the noise voltage cancelling most of the noise overall. In open wire telegraph applications this was referred to as the transposition theorem. However, the midpoint is never exact due to fabrication tolerance issues. [0039] Figure 6 is a block diagram schematically illustrating aspects of crosstalk

25 compensation system in accordance with the present disclosure. As described above, conductive traces 170 are situated on a PCB substrate 172. A capacitive coupling system 176 is positioned proximate the conductive traces 170 to selectively adjust capacitance to compensate for the imbalance in the signal traces 172 caused, for example, by fabrication instability. [0040] Since the magnitude of coupling capacitance is very small, some examples of the capacitive coupling system 176 disclosed herein use an application specific integrated circuit (ASIC) to adjust or compensate for the imbalance in signal traces. The ASIC is positioned across the signal paths but is galvanically isolated by a dielectric interface. The 5 dielectric can be a layer of HfO ₂ or SiO ₂ or an equivalent. Inside the ASIC is an array or metal (or semiconductor) pads that are positioned above each signal path to form a finite capacitor. [0041] Figure 7 is a schematic top view, and Figures 8A and 8B are end views conceptually illustrating aspects of an ASIC 180 in accordance with the present disclosure. 10 Figure 7 shows pads 182 positioned above the signal paths 170 for the 4,5 and 3,6

conductors of the connector 100. The pads 182 are connected to switches 184 via a conductive linkage or path 186. Figures 8A and 8B illustrate further aspects of the ASIC 180, which includes a housing 190 surrounding a semiconductor die 192. The pads 182 are situated on a dielectric layer 194 such as SiO ₂ , HfO ₂ , etc., and a first side 194a of the 15 dielectric layer 194 is positioned over the conductive paths 170. The pads 182 are

positioned on a second side 194b of the dielectric layer 194 opposite the first side 194a. Figure 8A conceptually shows the physical implementation of the ASIC 180 positioned over the signal paths 170, and Figure 8B illustrates the electrical equivalent. Figure 7 further illustrates an example of the distribution of the coupling capacitance along the 20 length of the signal paths 170. When the switch 184 is activated, an electrical path is created between the corresponding pads 182 and a finite coupling capacitance is added between the signal paths 170 as shown in Figure 8B. [0042] In this manner, capacitance can be added incrementally along the length of the signal paths 170 while keeping the ASIC 180 electrically isolated. Using a lumped 25 parameter can cause a resonance effect to occur at specific frequencies. As shown in Figure 8B, each linkage 186 between the pads 182 connects two capacitors 152, 188 in series with a total capacitance equal to C _ASIC /2. However, since the capacitors 188 are distributed along the length of the signal path 170, the effect is additive but not lumped. The total capacitance added between two signal paths 170 is nC _ASIC /2 where n is the 30 number if linkages 186 that have been activated or turned on using the associated switches 184. Once the desired capacitance has been added, the switches 184 can be fused or latched in a permanent ON state. In some examples, battery technology is used inside to the ASIC 180 so the switches 184 are not permanently fused allowing the compensation to be repeatedly changed. In other envisioned embodiments, MEMS technology is employed to create low resistance switches 184 that can be toggled to allow repetitive compensation. [0043] An example of the architecture of the ASCI 180 is shown in Figure 9. The 5 illustrated ASIC 180 includes the dielectric interface layer 194 that is situated proximate the conductive traces 170, substrate 172, etc. One or more metal layers 216 include the pads 182 and interconnecting links 186, and is positioned over the dielectric layer 194. One or more switch layers 214 that include the switches 184 are situated over the metal layer 216. A logic control layer 212 provides matrix decoding for switch selection, and 10 may contain a microcontroller core or simple I2C address decoding system. An

input/output (IO) interface layer 210 is situated over the logic control layer 212 for communicating with external devices such as a computer or other processing device. [0044] Figure 10 is a flow diagram illustrating an example of a compensation process using the disclosed compensation system 176. In block 230, crosstalk is measured 15 between preselected conductor pairs (e.g., 4,5– 3,6). If the coupling capacitances are not balanced as determined in decision block 232, the required additional capacitance is determined in block 235, and the required capacitance is added in block 236 by operating the switches 184. The process then returns to block 230 and repeats until decision block 232 determines the circuit is balanced. In some implementations, the process then 20 continues by fusing the switches 184 in block 240, and the crosstalk is again measured in block 242 to validate the compensation process. [0045] Various modifications and alterations of this disclosure may become apparent to those skilled in the art without departing from the scope and spirit of this disclosure, and it should be understood that the scope of this disclosure is not to be unduly limited to the 25 illustrative examples set forth herein.