Title:
CAPACITOR ARRAY FORMING METHOD AND SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/279520
Kind Code:
A1
Abstract:
The present disclosure provides a capacitor array forming method and a semiconductor structure. The capacitor array forming method comprises: providing a substrate, comprising an array region and a non-array region, a base layer and a dielectric layer being formed in the substrate, and a first barrier layer being formed between the base layer and the dielectric layer; forming, on a surface of the dielectric layer, a first array definition layer and a second array definition layer respectively corresponding to the array region and the non-array region; forming a pattern transfer layer on a surface of the first array definition layer and a surface of the second array definition layer; taking the pattern transfer layer as a mask, and patterning the dielectric layer and the second array definition layer to form a capacitor array located in the array region; and removing the remaining second array definition layer.
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Inventors:
WAN QIANG (CN)
Application Number:
PCT/CN2021/117449
Publication Date:
January 12, 2023
Filing Date:
September 09, 2021
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/033; H01L21/82; H01L27/08
Foreign References:
| CN112736035A | 2021-04-30 | |||
| CN108538835A | 2018-09-14 | |||
| CN112750783A | 2021-05-04 | |||
| CN108933140A | 2018-12-04 | |||
| CN110707044A | 2020-01-17 | |||
| US20190341252A1 | 2019-11-07 |
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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