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Patent Searching and Data


Title:
CAPACITOR ARRAY STRUCTURE AND FORMING METHOD THEREFOR
Document Type and Number:
WIPO Patent Application WO/2021/179926
Kind Code:
A1
Abstract:
The present application relates to a capacitor array structure and a forming method therefor. The forming method for the capacitor array structure comprises the following steps: providing a substrate, wherein a capacitor contact is exposed on the surface of the substrate, and the substrate comprises an array region and a peripheral region; forming a bottom support layer covering the substrate and the capacitor contact, wherein a gap is provided in the bottom support layer; forming a filling layer filling the gap and covering the capacitor contact and the surface of the bottom support layer, wherein the thickness of the filling layer located in the peripheral region is greater than the thickness of the filling layer located in the array region; forming support layers and sacrificial layers alternately stacked in a direction perpendicular to the substrate; forming a capacitor hole; and sequentially forming a lower electrode layer on the inner wall of the capacitor hole, a dielectric layer on the surface of the lower electrode layer and an upper electrode layer on the surface of the dielectric layer, so as to form a capacitor. The present application alleviates a delay effect of the capacitor array structure.

Inventors:
SHENG CHAOJUN (CN)
HU WENJIA (CN)
Application Number:
PCT/CN2021/078406
Publication Date:
September 16, 2021
Filing Date:
March 01, 2021
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/768; H01L21/77; H01L23/522; H01L23/532; H01L27/08
Foreign References:
CN209087830U2019-07-09
US20040197991A12004-10-07
CN207517677U2018-06-19
CN109065521A2018-12-21
CN109065501A2018-12-21
Attorney, Agent or Firm:
SHANGHAI WINSUN INTELLECTUAL PROPERTY AGENCY (CN)
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