Title:
CAPACITOR AND METHOD FOR MANUFACTURING CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2023/149313
Kind Code:
A1
Abstract:
Provided is a capacitor and a method for manufacturing the capacitor, in which the voltage dependence of the capacity can be reduced. The capacitor (1) comprises a silicon substrate (2), an electrically conductive layer (3), a dielectric layer (4), and an electrode layer (5). The silicon substrate (2) has a first main surface (21), and a second main surface (22) on the opposite side from the first main surface (21). The silicon substrate (2) has a porous silicon region (23) including a plurality of pores (24) formed in the first main surface (21). The electrically conductive layer (3) is formed along the surface (231) of the porous silicon region (23). The dielectric layer (4) has a shape conforming to the surface (231) of the porous silicon region (23), and is formed over the electrically conductive layer (3). The electrode layer (5) is formed over the dielectric layer (4).
Inventors:
FUJITA TOMOHIRO
HAGIHARA YOSUKE
YOSHIDA KAZUSHI
HAGIHARA YOSUKE
YOSHIDA KAZUSHI
Application Number:
PCT/JP2023/002314
Publication Date:
August 10, 2023
Filing Date:
January 25, 2023
Export Citation:
Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H01L27/04; H01L21/822
Domestic Patent References:
| WO2019021817A1 | 2019-01-31 | |||
| WO2020184517A1 | 2020-09-17 |
Foreign References:
| JP2021150552A | 2021-09-27 |
Attorney, Agent or Firm:
HOKUTO PATENT ATTORNEYS OFFICE (JP)
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