CHIP CACHE SYSTEM, DATA PROCESSING METHOD, DEVICE, STORAGE MEDIUM, AND CHIP

WIPO Patent Application WO/2023/124304

A1

Provided in the present disclosure are a chip cache system, a data processing method and apparatus, a device, a storage medium, and a chip. The cache system comprises: a plurality of operation subsystems, wherein each operation subsystem comprises at least one operation unit and at least one local shared buffer; each operation unit is connected to any local shared buffer in the operation subsystem where the operation unit is located; the local shared buffers are used for caching operation data read by the operation units in the operation subsystem to which the local shared buffers belong; and the operation units are used for accessing, on the basis of a generated access request, a local shared buffer, which matches an access address indicated by the access request, in the operation subsystem, and performing an operation on the basis of the read operation data when operation data indicated by the access request is read from the accessed local shared buffer.

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WO/2023/121771	DISTRIBUTED COMPRESSION/DECOMPRESSION SYSTEM
JP2023145337	CACHE COHERENCY PROTOCOL FOR ENCODING CACHE LINE BY DOMAIN SHARING STATE

WANG WENQIANG (CN)
XIA XIAOXU (CN)
ZHU ZHIQI (CN)
XU NINGYI (CN)

PCT/CN2022/121033

July 06, 2023

September 23, 2022

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SHANGHAI SENSETIME INTELLIGENT TECH CO LTD (CN)

G06F12/084

CN114297098A	2022-04-08
CN104981786A	2015-10-14
CN107291629A	2017-10-24
CN104699631A	2015-06-10
US20120233409A1	2012-09-13

BEIJING BESTIPR INTELLECTUAL PROPERTY LAW CORPORATION (CN)

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