Title:
CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD, AND PACKAGING METHOD FOR SEMICONDUCTOR STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2023/040144
Kind Code:
A1
Abstract:
The present application provides a chip packaging structure and a manufacturing method, and a packaging method for a semiconductor structure, and relates to the technical field of semiconductors, solving the technical problem of low chip yield. The chip packaging structure comprises: a chip, an intermediate insulating layer disposed on the chip, and a non-conductive adhesive layer disposed on the intermediate insulating layer. The chip is provided with a plurality of conductive protrusions, each of the conductive protrusions penetrating through the intermediate insulating layer. The intermediate insulating layer is provided with at least one group of accommodating holes, and the non-conductive adhesive layer fills the accommodating holes so that recesses matching the accommodating holes are formed on the non-conductive adhesive layer on the surface facing away from the intermediate insulating layer. A portion of non-conductive adhesive in the non-conductive adhesive layer overflows from the non-conductive adhesive layer at a first preset temperature and a preset pressure and flows into the recesses to prevent the non-conductive adhesive from overflowing from the edge of the chip, thereby improving the chip yield.
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Inventors:
FAN ZENGYAN (CN)
Application Number:
PCT/CN2022/071277
Publication Date:
March 23, 2023
Filing Date:
January 11, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/54; H01L23/485; H01L21/60; H01L21/603
Foreign References:
| CN106206510A | 2016-12-07 | |||
| CN110416170A | 2019-11-05 | |||
| JP2015056480A | 2015-03-23 | |||
| JP2012074449A | 2012-04-12 | |||
| US20160005707A1 | 2016-01-07 |
Attorney, Agent or Firm:
LEADER PATENT & TRADEMARK FIRM (CN)
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