Title:
CHIP SEPARATION METHOD AND WAFER
Document Type and Number:
WIPO Patent Application WO/2021/170145
Kind Code:
A1
Abstract:
A chip separation method, comprising: providing an array substrate (10), which comprises a bottom plate (11) and a plurality of chip units (12) having hole channels, wherein the plurality of chip units (12) are distributed on the bottom plate (11) at intervals; depositing a solid-phase medium (20) having a predetermined thickness on the array substrate (10), and filling the hole channels with the solid-phase medium (20); bonding a cover plate (30) on the array substrate (10), wherein the cover plate (30) covers the chip units (12) to form a wafer; cutting the wafer and forming a plurality of cutting bodies, wherein each cutting body comprises chip units (12); and removing the solid-phase medium (20) from the cutting bodies to form chips having the hole channels. The chip separation method can meet the cutting and forming requirements of chips, and prevent chippings from entering the hole channels of the chips, thereby guaranteeing the performance of the chips. Further provided is the wafer.
Inventors:
NIE YONGZHONG (CN)
LIU XIAOMIN (CN)
LIN ZUJIAN (CN)
YE XINWEN (CN)
XU CAIYUAN (CN)
LIU XIAOMIN (CN)
LIN ZUJIAN (CN)
YE XINWEN (CN)
XU CAIYUAN (CN)
Application Number:
PCT/CN2021/078527
Publication Date:
September 02, 2021
Filing Date:
March 01, 2021
Export Citation:
Assignee:
FATRI UNITED TESTING & CONTROL QUANZHOU TECH CO LTD (CN)
International Classes:
H01L21/78; B81C1/00
Foreign References:
| CN111320133A | 2020-06-23 | |||
| CN104192791A | 2014-12-10 | |||
| CN109920732A | 2019-06-21 | |||
| CN107731726A | 2018-02-23 | |||
| US20070160502A1 | 2007-07-12 | |||
| CN110091074A | 2019-08-06 |
Attorney, Agent or Firm:
BEIJING EAST IP LTD. (CN)
Download PDF:
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