Title:
CHIP SHARED RESOURCE SERIAL TEST DEVICE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2021/169317
Kind Code:
A1
Abstract:
A chip shared resource serial test method, comprising the following steps: S01: simultaneously connect a chip A and a chip B to a test platform by means of a double-throw relay; S02: the test platform inputs occupation time of each test item in each chip; S03: the test platform controls the double-throw relay to be connected to the chip A, and when the idle time of the test item X of the chip A is greater than the test time of one or more test items of the chip B, proceed to step S04; otherwise, the test platform tests each test item of the chip A in sequence, after the test is completed, the test platform controls the double-throw relay to be connected to the chip B, and the test platform tests the chip B; S04: the test platform controls the double-throw relay to be connected to the chip B, and the test platform tests one or more test items of the chip B; and S05: the test platform controls the double-throw relay to be connected to the chip A, and return to step S03. The present scheme can save the chip test time.
Inventors:
XUE LEO (CN)
Application Number:
PCT/CN2020/120804
Publication Date:
September 02, 2021
Filing Date:
October 14, 2020
Export Citation:
Assignee:
SHANGHAI NCATEST TECH CO LTD (CN)
International Classes:
G01R31/28
Domestic Patent References:
| WO2008033971A2 | 2008-03-20 |
Foreign References:
| CN111273157A | 2020-06-12 | |||
| CN106353667A | 2017-01-25 | |||
| CN105911462A | 2016-08-31 | |||
| CN102473462A | 2012-05-23 | |||
| CN209117739U | 2019-07-16 | |||
| CN102869998A | 2013-01-09 | |||
| CN104219003A | 2014-12-17 | |||
| US20070167785A1 | 2007-07-19 | |||
| US20140074423A1 | 2014-03-13 | |||
| JP2001004716A | 2001-01-12 | |||
| JP5526910B2 | 2014-06-18 | |||
| US7106073B1 | 2006-09-12 |
Other References:
WANG, LEI: "System Construction and Simulation Evaluation of Distributed ATS", NATIONAL DEFENSE INDUSTRY PRESS, 31 May 2019 (2019-05-31), ISBN: 7-118-11738-7
AGRAWAL V D: "Design of mixed-signal systems for testability", VLSI JOURNAL, no. 26, 31 December 1998 (1998-12-31), ISSN: 0167-9260
AGRAWAL V D: "Design of mixed-signal systems for testability", VLSI JOURNAL, no. 26, 31 December 1998 (1998-12-31), ISSN: 0167-9260
Attorney, Agent or Firm:
SHANGHAI TIANCHEN INTELLECTUAL PROPERTY AGENCY (CN)
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