Title:
CIRCUIT CONVERSION METHOD, LATCH CIRCUIT, AND C ELEMENT CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2023/157491
Kind Code:
A1
Abstract:
A circuit conversion method according to one embodiment of the present disclosure comprises: setting a processing target path in an asynchronous logic circuit; a first process for determining, for each of a plurality of logic cells in the processing target path, whether or not a glitch will occur; a second process for performing a conversion process of converting at least one logic cell for which it has been determined in the first process that a glitch will occur into at least one glitch suppression logic cell that performs a logic operation identical to that of said at least one logic cell and that is capable of suppressing the glitch; and a third process for determining, after the second process, whether or not a glitch will occur in a circuit downstream of the processing target path.
Inventors:
KABA YUJI (JP)
TANIMOTO TADAAKI (JP)
TANIMOTO TADAAKI (JP)
Application Number:
PCT/JP2022/048260
Publication Date:
August 24, 2023
Filing Date:
December 27, 2022
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G06F30/35; G06F30/33; H03K3/356
Domestic Patent References:
| WO2020129119A1 | 2020-06-25 |
Foreign References:
| JP2018142235A | 2018-09-13 | |||
| US20130174107A1 | 2013-07-04 | |||
| US11023636B1 | 2021-06-01 | |||
| JP2008065457A | 2008-03-21 |
Attorney, Agent or Firm:
TSUBASA PATENT PROFESSIONAL CORPORATION (JP)
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