Description

Technical Filed

The present invention relates to a circuit for converting a signal between digital and analog, a test apparatus for testing a device under test, and a method for converting a signal between digital and analog.

Background of the invention

As an operation rate of state-of-the-art devices increases, the challenge of evaluating the performance of such devices in production-scale quantities becomes progressively more difficult. One difficulty seems from conventional modes of testing high speed devices, which, at higher frequencies, tend to reflect the combined performance of the device under test (DUT) and the test hardware, rather than the performance of the DUT alone.

When testing high speed and high performance devices in the GHz (gigahertz) frequency range, the limiting factor for performance on conventional automatic test equipment (ATE) is determined more and more by jitter in the stimulus and conversion (sampling) clock signal of the analog-to-digital-converters (ADCs) and digital-to-analog-converters (DACs) that are part of the test hardware. Jitter is the time variation of a periodic signal, often in relation to a reference clock source. Jitter may be observed in characteristics such as a frequency of successive pulses, or a phase of periodic signals. In respect to performance of ATE, however, a common assumption is that the limiting effect is caused by jitter in the conversion clock alone. Therefore, high costs and high development efforts are commonly expended in providing ultra-low jitter clocks, e.g., by developing low-jitter clock generators incorporating sophisticated phase-locked-loop (PLL) architectures.

Recently, ADCs and DACs are produced for continuous operation on a fixed sample rate. That is, when ADCs and DACs are used in continuous mode, the converter sample rate is locked to the data rate with a PLL. All frequencies for converting the signals are usually known and therefore, it is possible to use the digital signal processor (DPS) to convert from an arbitrary user data rate to the converter rate. It is possible to do the same in burst mode, for example shown as Fig. 8. However, it is required to setup the PLL before each measurement in order to align the clock timing as shown in Fig. 9. That is, it is required to achieve accurate timing of the burst in a sub-converter-rate resolution. Conventional circuit for converting a signal, for example, a circuit shown in Fig.7 as a diagram requires one PLL for each channel. The simplest configuration of the PLL comprises a phase comparator, a loop filter and a voltage controlled oscillator; however, in general, PLL requires special and expensive external components. In addition, low jitter PLL cannot be integrated on CMOS process and therefore, PLLs consume a lot of board space. The time required for the PLL to settle before each burst is also an issue on ATE, where testing often consists of a large number of relatively short bursts.

Hence, it is an object of the present invention to provide an improved concept for a circuit for converting a signal in a burst mode.

This object is solved by a circuit for converting a signal between digital and analog according to claim 1 , a test apparatus for testing a device under test according to claim 15 and a method for converting a signal between digital and analog according to claim 18.

Some embodiments of the present invention also provide a computer program for carrying out steps of the inventive method.

Summary of the invention

According to a first aspect of the present application, a circuit for converting a signal between digital and analog, e.g., between a digital representation and an analog representation, i.e., from a digital representation to an analog representation or from an analog representation to a digital representation, the circuit comprising: a processor configured to provide or use a synchronizing clock signal, e.g. which is a clock signal to indicate a timing for outputting data based on an input data value associated with a sample time on a time grid or time axis, e.g. equally spaced in terms of time; a converter configured to convert a data between digital and analog using a converter clock signal, e.g. which is a clock signal to indicate a timing for receiving a piece of data provided from the processor and/or define a time when conversion between digital and analog is executed; a phase comparator, e.g. coupled to the processor to receive the synchronizing clock signal, and coupled to the converter to receive the converter clock signal, wherein the phase comparator is configured to determine a phase relationship between the synchronizing clock signal and the converter clock signal, i.e. the phase comparator is configured to perform comparison of timing of a rising edge or a falling edge between the synchronizing clock signal and the converter clock signal, thereby performing phase comparison between the signals; and a digital signal processor coupled to the phase comparator to receive an information about the phase relationship, e.g. phase difference between the synchronizing clock signal and the comparator clock signal, wherein the digital signal processor is configured to apply a delay to a signal data, e.g. time discrete output value associated with a different sample time, e.g. not on the original time grid or time axis, exchanged between the processor and the converter, e.g. in order to at least partially compensate for a phase difference between the synchronizing clock signal and the converter clock signal, in dependence of the phase relationship, wherein there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal, e.g. which is locked at the predetermined value.

According to embodiments of the present application, the circuit is configured to decide, on the basis of an information about the phase relationship between the synchronizing clock signal and the converter clock signal, whether an enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at a rising edge or at a falling edge of the converter clock signal, in order to obtain an enable signal which is in temporal synchronism with the converter clock signal.

According to the embodiments of the present application, the circuit is configured to select, in dependence on the information about the phase relationship between the synchronizing clock signal and the converter clock signal, between a first mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at edges of a first edge type, e.g. at falling edges, of the converter clock signal, to obtain an intermediate signal, and in which the intermediate signal is sampled at edges of a second edge type, e.g. rising edges, of the converter clock signal, to obtain the enable signal which is in temporal synchronism with the converter clock signal, and a second mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at edges of the second edge type of the converter clock signal, to obtain the enable signal which is in temporal synchronism with the converter clock.

According to the embodiments of the present application, the circuit comprises: a first flip- flop circuit coupled to the processor to receive an enable signal, e.g. which is a test signal on a different clock domain as the converter clock signal and provided from the processor for aligning the output timing of the signal data, wherein the first flip-flop circuit is configured to sample the enable signal at a first sampling phase, when the phase relationship indicates that a value of a phase difference between the synchronizing clock signal and the converter clock signal is in a first predetermined range, e.g. smaller than a predetermined value, in case the phase difference has a potential risk to lead to metastability, the phase of sampling the enable signal is inverted to move sampling time instances away from clock edges of the synchronization clock signal, to obtain a sampled signal; a signal selector coupled to the processor to receive the enable signal and coupled to the first flip-flop circuit to receive the sampled signal, wherein the signal selector is configured to select one of the received signals, e.g. in dependence on the phase relationship, to obtain a selected signal; a second flip-flop circuit coupled to the signal selector to receive the selected signal, wherein the second flip-flop circuit is configured to sample the enable signal at a second sampling phase, when the phase relationship is in a second predetermined range, e.g. which is different from the first predetermined range and typically non-overlapping with the first predetermined range, and which may, for example, indicate that a value of a phase difference between the synchronizing clock signal and the converter clock signal is larger than a predetermined value; in this case, the edge of the sampled signal is synchronized with the converter clock signal, i.e. output timing of the signals are aligned and therefore, it is not necessary to align the rising timing of the clock signal; and a first-in-first-out circuit coupled to the digital signal processor to receive the signal data, and coupled to the second flip-flop circuit via a delay circuit, e.g. which calculates delay time based on the phase difference between the enable signal and the converter clock signal, to receive a delayed version of an output signal of the second flip-flop circuit, e.g. which indicates a signal data output timing of the converter, wherein the first-in-first-out circuit provides signal data associated with the sampled enable signal to the converter.

According to the embodiments of the present application, the selector comprises a multiplexer, wherein the multiplexer selects one of input signals based on the information about the phase relationship. In addition, the phase comparator comprises a phase-to- digital converter, wherein the phase-to-digital converter is configured to measure a phase difference between the synchronizing clock signal and the converter clock signal for determining the phase relationship. Furthermore, the digital signal processor, e.g. a fractional delay filter, is configured to counteract and/or at least partially compensate a phase difference between the synchronizing clock signal and the converter clock signal. According to the embodiments of the present application, the digital signal processor, e.g. a fractional delay filter, is configured to provide a filtered data value associated with a conversion time in a time grid determined by the converter clock signal, e.g. signal sample, which is actually digital-to-analog converted by the converter at a time determined by the converter clock signal, on the basis of one or more input data values provided in synchronism with the synchronizing clock signal, e.g. one or more signal samples provided by the processor which should be digital-to-analog converted at times determined by the synchronizing clock signal, which is, not possible due to the time shift/phase shift between the synchronizing clock signal and the converter clock signal; and/or wherein the digital signal processor, e.g. a fractional delay filter, is configured to provide filtered data values aligned to a time axis determined by the synchronizing clock signal on the basis of one or more data values defined in a time grid determined by the converter clock signal, e.g. one or more signal samples which have actually been analog-to-digital converted by the converter at times determined by the converter clock signal, but which should have been analog-to-digital converted at times determined by the synchronizing clock signal, which is, however, not possible due to the time shift/phase shift between the synchronizing clock signal an the converter clock signal.

According to the embodiments of the present application, the digital signal processor or the fractional delay filter uses a Farrow structure. But any other suitable means for implementing a delay is permissible. The circuit comprises an oscillator, wherein an output signal of the oscillator is used as the converter clock signal or wherein the circuit is configured to derive the converter clock signal from the output signal of the oscillator. The circuit is configured to derive the synchronizing clock signal and the converter clock signal from a common reference signal, such that frequencies of the synchronizing clock signal and of the converter clock signal are in a predetermined relationship. The converter is a digital-to-analog or an analog-to-digital converter.

According to a second aspect of the present application, a test apparatus fortesting a device under test, comprising the circuit according to the present application. The test apparatus is configured to perform, e.g. start a test flow, e.g. a test flow using multiple channel modules providing signals to the device under test and evaluating signals received from a device under test, in synchronism with the synchronizing clock signal. The test apparatus is configured to provide an analog signal obtained using the converter on the basis of input signal values, e.g. provided by the processor, to the device under test, e.g. thereby stimulating the device under test, and/or wherein the apparatus is configured to obtain digital data provided by the digital signal processor on the basis of a digitized device-undertest signal obtained from the converter using the delay and to evaluate the digital data, e.g. to characterize the device under test.

According to a third aspect of the present application, a method for converting a signal between digital and analog, the method comprising: receiving a synchronizing clock signal provided from a processor or used by a processor and a converter clock signal used by a converter; determining a phase relationship between the synchronizing clock signal and the converter clock signal; and applying a delay to a signal data exchanged between the processor and the converter based on the phase relationship between the synchronizing clock signal and the converter clock signal, wherein there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal.

According to an embodiment of the present application, the method comprises; selecting, in dependence on the phase relationship between the synchronizing clock signal and the converter clock signal, between a first mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock, is sampled at edges of a first edge type of the converter clock, to obtain an intermediate signal, and in which the intermediate signal is sampled at edges of a second edge type of the converter clock, to obtain the enable signal which is in temporal synchronism with the converter clock, and a second mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock, is sampled at edges of the second edge type of the converter clock, to obtain the enable signal which is in temporal synchronism with the converter clock; and providing the signal data associated with the sampled enable signal to the converter.

According to a fourth aspect of the present application, computer program is provided, wherein the computer program is configured to implement the above described method, when being executed on a computer or micro controller, so that the above described method is implemented by the computer program.

Brief Description of the Figures

In the followings, embodiments of the present application are described in more detail with reference to the figures in which: Fig. 1 shows a schematic block diagram of a circuit for converting a signal according to a first embodiment of the present invention of the present application;

Fig. 2 shows a schematic timing diagram of a phase comparator according to the first embodiment of the present invention of the present application;

Fig. 3 shows a schematic block diagram of the phase comparator according to Fig.2 in accordance with the present invention concept of the present application;

Fig.4 shows a schematic illustration indicating the phase relationship between the synchronizing clock and the converter clock according to the first embodiment of the present invention concept of the present application;

Fig. 5 shows a schematic block diagram indicating an implementation example of the circuit according to a second embodiment of the present invention of the present application;

Fig. 6 shows a schematic block diagram indicating a test apparatus for testing a device under test according to a third embodiment of the present invention concept of the present application;

Fig. 7 shows a flowchart indicating steps of a method for converting a signal between digital and analog according to a third embodiment of the present invention concept of the present application;

Fig. 8 shows a schematic block diagram according to a prior art; and

Fig. 9 shows a schematic timing diagram according to a prior art.

Detailed Description of the Embodiments

The following description sets forth specific details such as particular embodiments, procedures, techniques etc. for purpose of explanation and not limitation. It will be appreciated by those skilled in the art that other embodiments may be employed apart from these specific details. For example, although the following description is facilitated using non-limiting example applications, the technology may be employed to any type of converters. In some instances, detailed description of well-known methods, interfaces, circuits and devices are omitted so as not to obscure the description with unnecessary detail.

Equal or equivalent elements with equal or equivalent functionality are denoted in the following description by equal or equivalent reference signs.

Fig. 1 shows a schematic block diagram of a circuit for converting a signal according to a first embodiment of the present invention. A circuit 100 comprises a processor 2, a converter 4, a phase comparator, PDC, 6 and digital signal processor, DSP, 8.

The processor 2 is coupled to the PDC 6 and provides a synchronizing clock signal to the PDC 6. In addition, the processor 2 is coupled to the DSP 8 and provides a data / signal data to the DSP 8. The processor 2 is configured to provide or use a synchronizing clock signal, e.g. which is a clock signal to indicate a timing for outputting a data based on an input data value associated with a sample time on a time grid or time axis, e.g. equally spaced in terms of time. In this embodiment, it is depicted that the synchronizing clock signal is provided from the processor 2 to the PDC 6. However, the synchronizing clock signal may be provided to the processor 2 from another data source. In this case, the processer 2 uses the provided synchronizing clock signal.

The converter 4 is coupled to the PDC 6 and provides converter clock signal to the PDC 6. In addition, the converter 4 is coupled to the DSP 8 and receives signal data via the DSP 8 provided by the processor 2. The converter 4 is configured to convert a data between digital and analog using a converter clock signal, e.g. which is a clock signal to indicate a timing for receiving a data provided from the processor and/or define a time when conversion between digital and analog is executed. The converter 4 is a digital-to-analog or an analog- to-digital converter.

The PDC 6 is coupled to the processor 2 to receive the synchronizing clock signal, and coupled to the converter 4 to receive the converter clock signal and the PDC 6 is configured to perform comparison of timing of a rising edge or a falling edge between the synchronizing clock signal and the converter clock signal, thereby performing phase comparison between the signals. That is, the PDC 6 detects the phase difference between the synchronizing clock signal and the convert clock signal. In addition, the PDC 6 comprises a phase-to-

:> digital converter, wherein the phase-to-digital converter is configured to measure a phase difference between the synchronizing clock signal and the converter clock signal for determining the phase relationship.

The DSP 8 is coupled to the PDC 6 to receive an information about the phase relationship, e.g. phase difference between the synchronizing clock signal and the converter clock signal, and the DSP 8 is configured to apply a delay to a signal data, e.g. time discrete output value associated with a different sample time, e.g. not on the original time grid or time axis, exchanged between the processor and the converter, e.g. in order to at least partially compensates for a phase difference between the synchronizing clock signal and the converter clock signal, in dependence of the phase relationship, wherein there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal, e.g. which is locked at the predetermined value. Furthermore, the DSP 8 is configured to counteract and/or at least partially compensate a phase difference between the synchronizing clock signal and the converter clock signal.

In the circuit 100, there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal, e.g. is locked at the predetermined value. The predetermined frequency relationship is defined based on the required result or running condition of the circuit or any other criteria.

As described above, the processor 2 provides the signal data to the DSP 8 and the synchronizing clock signal to the PDC 6. The PDC 6 receives the converter clock signal from the converter 4 and determines a phase relationship between the synchronizing clock signal and the converter clock signal. Information about the determined phase relationship is provided from the PDC 6 to the DSP 8. Then, the DSP 8 applies a delay to the signal data exchanged between the processor 2 and the converter 4, in dependence of the phase relationship. Hence, the output timing difference cause by the fact that the converter clock signal is phase shifted against the synchronizing clock signal is corrected at the converter 4.

Fig. 2 shows a schematic timing diagram of the PDC 6 and Fig. 3 shows a schematic block diagram of the PDC 6. As shown in Figs. 2 and 3, a reference clock signal REFCLK/REF_CLK and a measurement clock signal MEAS_CLK are provided to the PDC 6. Then, the PDC 6 delivers the delay between rising REF_CLK edge, i.e. rising edge of the reference clock signal, to rising MEAS_CLK edge, i.e., the rising edge of the measurement clock signal. As described above, the PDC 6 determines the phase difference, i.e. delay of the signal, that is, the accuracy of the PDC 6 is directly influencing the timing accuracy of the circuit. Hence, the PDC 6 is required to be accurate.

Fig.4 shows a schematic illustration indicating the phase relationship between the synchronizing clock signal and the converter clock signal. The DSP 8, or as shown in Fig. 4, e.g. the fractional delay filtering which is included in the DSP 8, is configured to provide a filtered data value (signal sample) associated with a conversion time in a time grid determined by the converter clock signal, which is actually digital-to-analog converted by the converter at a time determined by the converter clock signal, on the basis of one or more input data values provided in synchronism with the synchronizing clock signal, e.g. one or more signal samples provided by the processor 2 which should be digital-to-analog converted at times determined by the synchronizing clock signal, which is, not possible due to the time shift/phase shift between the synchronizing clock signal and the converter clock signal and/or the DSP 8 or the fractional delay filtering, is configured to provide filtered data values aligned to a time axis determined by the synchronizing clock signal on the basis of one or more data values defined in a time grid determined by the converter clock signal, e.g. one or more signal samples which have actually been analog-to-digital converted by the converter at times determined by the converter clock signal, but which should have been analog-to-digital converted at times determined by the synchronizing clock signal, which is, however, not possible due to the time shift/phase shift between the synchronizing clock signal an the converter clock signal.

In addition, the PDC 6 is possible to be integrated into standard CMOS process, and therefore, it allows higher density when compared to the case of PLL approach in the known art. Furthermore, one central clock generation for all converter clocks, and hence, it allows also higher density. Another advantage is that usable PDC measurements are available in a time much shorter than the typical settling times of low phase noise PLLs.

Fig. 5 shows a schematic block diagram indicating an implementation of the circuit 200 according to a second embodiment of the present invention. As shown in Fig. 5, the circuit 200 further comprises a first flip-flop circuit, FF, 10, a signal selector, e.g. multiplexer 12, a second flip-flop circuit, FF, 14 and an oscillator, VCSO (voltage controlled SAW oscillator, SAW = surface acoustic wave), 16. In addition, the DSP 8 comprises a fractional delay filter, which can be implemented with a Farrow structure or use any other appropriate implementation. The first FF10 is coupled to the processor 2 for receiving an enable signal, TEST_EN, e.g. which is a test signal on the different clock domain as the converter clock signal and provided from the processor for aligning the output timing of the signal data, wherein the FF 10 is configured to sample the enable signal at a first sampling phase, when the phase relationship indicates that a value of a phase difference between the synchronizing clock signal and the converter clock signal is in a first predetermined range, e.g. smaller than a predetermined value, in case the phase difference has a potential risk to lead metastability, the phase of sampling the enable signal is inverted to move sampling time instances away from clock edges of the synchronization clock signal, to obtain a sampled signal. The predetermined range is determined, for example, based on the required accuracy of the test.

The signal selector, i.e., multiplexer 12 is coupled to the processor 2 for receiving the enable signal TEST_EN and coupled to the first FF 10 to receive the sampled signal, wherein the multiplexer 12 is configured to select one of the received signals, e.g. in dependence on the phase relationship, to obtain a selected signal, EN_SYNC. The multiplexer 12 selects one of input signals based on the information about the phase relationship.

The second FF 14 is coupled to the multiplexer 12 for receiving the selected signal EN_SYNC, wherein the second FF14 is configured to sample the enable signal TEST_EN at a second sampling phase, when the phase relationship is in a second predetermined range, e.g. which is different from the first predetermined range and typically nonoverlapping with the first predetermined range, and which may, for example, indicate that a value of a phase difference between the synchronizing clock signal and the converter clock signal is larger than a predetermined value; in this case, the edge of the sampled signal is synchronized with the converter clock signal, i.e. output timing of the signals are aligned and therefore, it is not necessary to align the rising timing of the clock signal.

In Fig. 4, it is depicted that the phase difference is determined based on the rising edge, however, as described, the circuit 200 is possible to select falling edges. That is, the circuit 200 is configured to select, in dependence on the information about the phase relationship between the synchronizing clock signal and the converter clock signal, between a first mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at edges of a first edge type, e.g. at falling edges, of the converter clock signal, to obtain an intermediate signal, and in which the intermediate signal is sampled at edges of a second edge type, e.g. rising edges, of the converter clock signal, to obtain the enable signal which is in temporal synchronism with the converter clock signal, and a second mode, in which the enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at edges of the second edge type of the converter clock signal, to obtain the enable signal which is in temporal synchronism with the converter clock.

The VCSO 16 is coupled to the converter 4. An output signal of the VCSO 16 is used as the converter clock signal. The circuit 200 is configured to derive the synchronizing clock signal and the converter clock signal from a common reference signal, such that frequencies of the synchronizing clock signal and of the converter clock signal are in a predetermined relationship. In addition, the circuit 200 may be configured to derive the converter clock signal from the output signal of the VCSO 16.

In addition, as shown in Fig. 5, a first-in-first-out circuit FIFO is coupled to the DSP 8 for receiving the signal data, and coupled to the second FF 14 via an additional Delay circuit (“Delay N”) that is used to delay the output signal of FF 14 by a programmable number of target clock signal cycles. The number of clock cycles is chosen in a way that the FIFO enable signal READ_EN is becoming active exactly at the correct point in time when enough data is available in the FIFO and the device under test is supposed to receive the data via the DAC, wherein the FIFO provides signal data associated with the sampled enable signal to the converter 4.

Furthermore, as shown in Fig. 5, the circuit 200 is configured to decide, on the basis of an information about the phase relationship between the synchronizing clock signal and the converter clock signal, whether an enable signal triggering a conversion of data between digital and analog, which is in temporal synchronism with the synchronization clock signal, is sampled at a rising edge or at a failing edge of the converter clock signal, in order to obtain an enable signal which is in temporal synchronism with the converter clock signal.

Fig. 6 shows a schematic block diagram indicating a test apparatus for testing a device under test according to a third embodiment of the present invention. In Fig. 6, the test apparatus including the circuit 200 according to the second embodiment, however, the test apparatus may include the circuit 100 according to the first embodiment. As indicated in Fig. 6, the PDC 6 further includes processing circuit to provide information regarding phase difference to the DSP 8 and the selector 12. The detailed explanation is omitted to avoid repeated explanation of the circuit of the present invention.

As shown in Fig. 6, in the test apparatus, beginning of the waveform is determined by signal (TEST_EN), e.g. start a test flow, e.g. a test flow using multiple channel modules providing signals to the device under test and evaluating signals received from a device under test, in synchronism with the synchronizing clock signal. Therefore, timing requirements at data interface is relatively relaxed.

In addition, the test apparatus, i.e. the circuit 200, is configured to provide an analog signal obtained using the converter 4 on the basis of input signal values, e.g. provided by the processor 2, to the device under test, e.g. thereby stimulate the device under test, and/or wherein the apparatus is configured to obtain digital data provided by the DSP 8 on the basis of a digitized device-under-test signal obtained from the converter 4 using the delay and to evaluate the digital data, e.g. to characterize the device under test.

Fig. 7 shows a flowchart indicating steps of a method for converting a signal between digital and analog according to a third embodiment of the present invention concept.

At the first, receiving a synchronizing clock signal and a converter clock signal (S10). That is, a phase comparator, i.e. the PDC 6 as shown in Fig. 1 or Fig. 2, for instance, receives the synchronizing clock signal from a processor, i.e. the processor 2 in Fig. 1 or Fig. 2, for instance, and the converter clock signal from the converter, i.e. the converter 4 in Fig. 1 or Fig. 2, for instance. The synchronizing clock may be provided by the processor 2 or by any other source.

Next, determining a phase relationship between the synchronizing clock signal and the converter clock signal (S12). Then, applying a delay to a signal data based on the phase relationship (S14). That is, applying a delay to a signal data exchanged between the processor and the converter based on the determined phase relationship between the synchronizing clock signal and the converter clock signal in step S12. In addition, there is a predetermined frequency relationship between the synchronizing clock signal and the converter clock signal.

Further to the steps mentioned above, it is possible to select a sampling edge mode. That is, the method further comprises a step to select the sampling edge mode, i.e. selecting between a first mode and a second mode in dependence on the determined phase relationship between the synchronizing clock signal and the converter clock signal. In the first mode, an enable signal, which is in temporal synchronism with the synchronization clock, is sampled at edges of a first edge type, e.g. at a falling edge, of the converter clock signal to obtain an intermediate signal and in which the intermediate signal is sampled at edge of a second edge type, e.g. rising edge, of the converter clock, to obtain the enable signal which is in temporal synchronism with the converter clock. In the second mode, the enable signal, which is in temporal synchronism with the synchronization clock, is sampled at edges of the second edge type, e.g. at the rising edge, to obtain the enable signal, which is in temporal synchronism with the converter clock. Then, the signal data associated with the sampled enable signal is provided to the converter, e.g. the converter 4 in Fig. 1 or Fig. 2

According to a fourth aspect of the present application, computer program is provided, wherein the computer program is configured to implement the above described method, when being executed on a computer or micro controller, so that the above described method is implemented by the computer program.

Although some aspects have been described in the context of an apparatus, it is clear that these aspects also represent a description of the corresponding method, where a block or device corresponds to a method step or a feature of a method step. Analogously, aspects described in the context of a method step also represent a description of a corresponding block or item or feature of a corresponding apparatus. Some or all of the method steps may be executed by (or using) a hardware apparatus, like for example, a microprocessor, a programmable computer or an electronic circuit. In some embodiments, one or more of the most important method steps may be executed by such an apparatus.

The inventive data stream can be stored on a digital storage medium or can be transmitted on a transmission medium such as a wireless transmission medium or a wired transmission medium such as the Internet.

Depending on certain implementation requirements, embodiments of the application can be implemented in hardware or in software. The implementation can be performed using a digital storage medium, for example a floppy disk, a DVD, a Blu-Ray, a CD, a ROM, a PROM, an EPROM, an EEPROM or a FLASH memory, having electronically readable control signals stored thereon, which cooperate (or are capable of cooperating) with a programmable computer system such that the respective method is performed. Therefore, the digital storage medium may be computer readable.

Some embodiments according to the invention comprise a data carrier having electronically readable control signals, which are capable of cooperating with a programmable computer system, such that one of the methods described herein is performed.

Generally, embodiments of the present application can be implemented as a computer program product with a program code, the program code being operative for performing one of the methods when the computer program product runs on a computer. The program code may, for example, be stored on a machine readable carrier.

Other embodiments comprise a computer program for performing one of the methods described herein, stored on a machine readable carrier.

In other words, an embodiment of the inventive method is, therefore, a computer program having a program code for performing one of the methods described herein, when the computer program runs on a computer.

A further embodiment of the inventive methods is, therefore, a data carrier (or a digital storage medium, or a computer-readable medium) comprising, recorded thereon, the computer program for performing one of the methods described herein. The data carrier, the digital storage medium or the recorded medium are typically tangible and/or nontransitionary.

A further embodiment of the inventive method is, therefore, a data stream or a sequence of signals representing the computer program for performing one of the methods described herein. The data stream or the sequence of signals may, for example, be configured to be transferred via a data communication connection, for example via the internet.

A further embodiment comprises a processing means, for example a computer, or a programmable logic device, configured to or adapted to perform one of the methods described herein.

A further embodiment comprises a computer having installed thereon the computer program for performing one of the methods described herein. A further embodiment according to the invention comprises an apparatus or a system configured to transfer (for example, electronically or optically) a computer program for performing one of the methods described herein to a receiver. The receiver may, for example, be a computer, a mobile device, a memory device or the like. The apparatus or system may, for example, comprise a file server for transferring the computer program to the receiver.

In some embodiments, a programmable logic device (for example a field programmable gate array) may be used to perform some or all of the functionalities of the methods described herein. In some embodiments, a field programmable gate array may cooperate with a microprocessor in order to perform one of the methods described herein. Generally, the methods are preferably performed by any hardware apparatus.

The apparatus described herein may be implemented using a hardware apparatus, or using a computer, or using a combination of a hardware apparatus and a computer.

The apparatus described herein, or any components of the apparatus described herein, may be implemented at least partially in hardware and/or in software.

The above described embodiments are merely illustrative for the principles of the present invention. It is understood that modifications and variations of the arrangements and the details description herein will be apparent to others skilled in the art. It is the intent, therefore, to be limited only by the scope of the impending patent claims and not by the specific details presented by way of description and explanation of the embodiments herein.