Title:
CIRCUIT, MULTIPLIER AND CIRCUIT OPTIMIZATION METHOD
Document Type and Number:
WIPO Patent Application WO/2023/124561
Kind Code:
A1
Abstract:
A circuit, a multiplier and a circuit optimization method, related to the field of electronic devices and used for realizing the balance between the power consumption and the precision of the multiplier. The circuit comprises a digital addition circuit and an analog addition circuit. The digital addition circuit is used for performing digital accumulation on bits belonging to a first bit range in a plurality of sets of partial products, wherein the plurality of sets of partial products are obtained by multiplying a plurality of first numerical values by a plurality of second numerical values respectively, the first bit range refers to S bits of a product value of a first numerical value and a second numerical value, S is a positive integer, and the product value is obtained by shifting a set of partial products and then accumulating same according to bits; and the analog addition circuit is used for performing analog accumulation on the analog quantity corresponding to the numerical value of each bit belonging to a second bit range in the plurality of sets of partial products, wherein the second bit range refers to T bits which are not overlapped with the first bit range of the product value, T is a positive integer, and S + T is smaller than or equal to the digit of the product value.
Inventors:
NI LEIBIN (CN)
WU ZHIHANG (CN)
WU WEI (CN)
MA SONG (CN)
WU ZHIHANG (CN)
WU WEI (CN)
MA SONG (CN)
Application Number:
PCT/CN2022/130963
Publication Date:
July 06, 2023
Filing Date:
November 09, 2022
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
G06F7/544
Foreign References:
| CN105808206A | 2016-07-27 | |||
| CN109643228A | 2019-04-16 | |||
| US6535901B1 | 2003-03-18 | |||
| US20210081175A1 | 2021-03-18 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT&TRADEMARK AGENT LTD. (CN)
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