Title:
CIRCUIT FOR PREVENTING LATCH-UP IN CMOS MEMORY CELL
Document Type and Number:
WIPO Patent Application WO2006011982
Kind Code:
B1
Abstract:
A CMOS circuit (40) is provided which includes a current-limiting device (46, 48) arranged along a power-supply bus (42) or a ground bus (44) of the circuit. The current-limiting device (46, 48) is configured to prevent latch up of the CMOS circuit (40). More specifically, the current-limiting device (46, 48) is configured to maintain a junction of the parasitic pnpn diode structure as reverse-biased. A method is also provided which includes creating a current-voltage plot of a pnpn diode arranged within a first CMOS circuit which is absent of a current-limiting device arranged along a power bus of the circuit. In addition, the method includes determining a holding current level from the current-voltage plot and sizing a current-limiting device to place along a power bus of a second CMOS circuit comprising similar design specifications as the first CMOS circuit such that the current through the second CMOS circuit does not exceed the holding current level.
Inventors:
KAPRE RAVINDRA M (US)
SHARIFZADEH SHAHIN (US)
SHARIFZADEH SHAHIN (US)
Application Number:
PCT/US2005/020800
Publication Date:
June 08, 2006
Filing Date:
June 13, 2005
Export Citation:
Assignee:
CYPRESS SEMICONDUCTOR CORP (US)
KAPRE RAVINDRA M (US)
SHARIFZADEH SHAHIN (US)
KAPRE RAVINDRA M (US)
SHARIFZADEH SHAHIN (US)
International Classes:
H01L27/092; G11C5/14; G11C11/34; H02H9/02
Download PDF: