Title:
CIRCUIT TIMING OPTIMIZATION METHOD BASED ON FLEXIBLE REGISTER TIMING LIBRARY
Document Type and Number:
WIPO Patent Application WO/2023/015878
Kind Code:
A1
Abstract:
Disclosed in the present invention is a circuit timing optimization method based on a flexible register timing library. Firstly, registers are respectively simulated by means of a plurality of groups of input signal conversion time, clock signal conversion time and register load capacitance, a corresponding clock-to-q delay at this time is obtained by means of changing setup slacks and hold slacks of the registers, and clock-to-q delays of the registers under specific input signal conversion time, clock signal conversion time, register load capacitance, setup slacks and hold slacks are obtained by means of linear interpolation, thereby establishing a flexible register timing library; and static timing analysis is then performed on all register paths in a circuit by using the library, and the minimum clock cycle which meets the condition of a setup time margin and a hold time margin both being greater than a zero condition is found by means of changing the setup slacks and hold slacks of the registers. Thus, the circuit performance is improved without changing the circuit design and without increasing the circuit area overhead.
Inventors:
CAO PENG (CN)
WANG JIAHAO (CN)
JIANG HAIYANG (CN)
WANG JIAHAO (CN)
JIANG HAIYANG (CN)
Application Number:
PCT/CN2022/079945
Publication Date:
February 16, 2023
Filing Date:
March 09, 2022
Export Citation:
Assignee:
UNIV SOUTHEAST (CN)
International Classes:
G06F30/337; G06F30/3315; G06F119/12
Foreign References:
| CN113673193A | 2021-11-19 | |||
| CN1985257A | 2007-06-20 | |||
| CN103324774A | 2013-09-25 | |||
| CN103632001A | 2014-03-12 | |||
| US6336205B1 | 2002-01-01 |
Attorney, Agent or Firm:
NANJING RUIHONG PATENT & TRADEMARK AGENCY (ORDINARY PARTNERSHIP) (CN)
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