BACKGROUND

Some embodiments described in the present disclosure relate to a processing circuitry and, more specifically, but not exclusively, to a processing circuitry for executing a loop of instructions.

As used herein, a processing unit may be any kind of programmable or non-programmable circuitry that is configured to carry out operations described below. The processing unit may comprise hardware as well as software. For example, the processing unit may comprise one or more processors and a transitory or non-transitory memory that carries a computer program which causes the processing unit to perform the respective operations when the program is executed by the one or more processors.

In addition, as used herein, the term “instruction” is used to mean “computer instruction” and the terms are used interchangeably.

A typical computer program comprises one or more sequences of computer instructions. Typically, processing circuitry executing a computer program executes a sequence of computer instructions in order. A branch instruction is a computer instruction that causes the processing circuitry to begin executing another sequence of computer instructions, thus deviating from execution of the sequence of computer instructions in order. The term “branching” refers to an act of switching execution to a different sequence of computer instructions as a result of executing a branch instruction.

In some computer programs flow of execution of the computer program is controlled using conditional branch instructions, where a branch instruction is executed subject to one or more conditions being satisfied. Such conditional branch instructions may be used to execute a sequence of instructions only when the one or more conditions are satisfied. Another use of conditional branch instructions is to control repeated execution of the sequence of instructions in a loop, i.e. in a plurality of loop iterations. When executing a loop of instructions, i.e. a sequence of computer instructions executed repeatedly in a plurality of instructions, there is a branch instruction to return execution to a first instruction of the loop of instructions when there is a need to start execution of another iteration of the loop. When there is no need to execute the loop an additional time, another instruction following the loop of instructions is executed.

The term “instruction pipelining” refers to instruction-level parallelism within a single processing unit. An instruction pipeline of a processing circuitry reads a computer instruction from memory while one or more previous computer instructions are being executed in other segments of the processing unit’s pipeline. Thus the processing unit may execute multiple computer instructions simultaneously. A common use of instruction pipelining is to increase throughput of a computer system.

When a sequence of instructions comprising a conditional branch instruction is executed using an instruction pipeline, there may be a need to fetch, i.e. read a computer instruction from memory, of a new instruction to execute after executing the conditional branch instruction before a result of executing the conditional branch instruction are known. Thus, there may be a need to fetch the new instruction before it is known whether one or more conditions of the branch are fulfilled or not, and thus before it is known whether the branch is executed (also known as “taken”), or not.

The term “branch prediction” refers to a computation aimed at predicting, before computing the one or more conditions of a conditional branch, whether the conditional branch is taken or not.

SUMMARY

It is an object of the present disclosure to describe a circuitry and a method for branch prediction.

The foregoing and other objects are achieved by the features of the independent claims. Further implementation forms are apparent from the dependent claims, the description and the figures.

According to a first aspect of the invention, a processing circuitry is for executing a loop of instructions in each of a plurality of iterations, the loop of instructions comprises a branch point instruction and a predicted loop count value, and in each of the plurality of iterations the processing circuitry: computes a predicted next instruction address using a slope value when a current instruction address of a current executed instruction equals a branch address of the loop’s branch point instruction, the slope value is indicative of an expected change in the predicted loop count value when executing the loop of instructions in another of the plurality of iterations, and provides the predicted next instruction address to at least one part of the processing circuitry for the purpose of retrieving a next instruction to execute.

According to a second aspect of the invention, a method is for executing a loop of instructions in each of a plurality of iterations, where the loop of instructions comprises a branch point instruction and a predicted loop count value, and each of the plurality of iterations comprises: computing a predicted next instruction address using a slope value when a current instruction address of a current executed instruction equals a branch address of the loop’s branch point instruction, the slope value is indicative of an expected change in the predicted loop count value when executing the loop of instructions in another of the plurality of iterations, and providing the predicted next instruction address to at least one part of a processing circuitry for the purpose of retrieving a next instruction to execute.

In an implementation form of the first and second aspects, the branch point instruction is an end instruction of the loop of instructions, and the branch address is an end instruction address of the end instruction. Optionally, the loop of instructions comprises a start instruction. Optionally, computing the predicted next instruction address comprises: when a current iteration count value of the loop of instructions is less than the predicted loop count value: incrementing the current iteration count value by one, and selecting a start instruction address of the loop’s start instruction as the predicted next instruction address; and when the current iteration count value of the loop is not less than the predicted loop count value: incrementing the predicted loop count value of the loop by the slope value, and selecting an instruction address consecutive to the current instruction address as the predicted next instruction address. Incrementing the predicted loop count value of the loop by the slope value when the current iteration count value of the loop is not less than the predicted loop count value (i.e. when executing the loop for a last time) increases likelihood that that the predicted loop count value in a following execution of the loop is equal an actual loop count value in the following execution of the loop, and thus increases accuracy of a predicted next instruction address.

In another implementation form of the first and second aspects, the processing circuitry further comprises a branch prediction table comprising a plurality of loop prediction entries, each describing one of a plurality of loops of instructions executed by the processing circuitry. Optionally, the start instruction address, the end instruction address, the predicted loop count value and the slope value are members of one of the loop prediction entries of the branch predichon table. Optionally, the processing circuitry further comprises at least one other part configured for computing the slope value according to a plurality of predicted loop count values of the plurality of loop prediction entries. Computing the slope value according to a plurality of values of the plurality of loop predictions entries, for example including the plurality of predicted loop count values, increases accuracy of the slope value, thus increasing accuracy of the predicted next instruction address.

In another implementation form of the first and second aspects, the processing circuitry is configured for executing a plurality of instructions, comprising a loop initialization instruction, and the slope value is an argument of the loop initialization instruction. Using a loop initialization instruction having the slope value as an argument facilitates computing the slope value externally to the processing circuitry for executing the loop, for example by a compiler processing source code, increasing accuracy of the slope value and thus increasing accuracy of the predicted next instruction address.

In another implementation form of the first and second aspects, the slope value is equal to or greater than zero. Optionally, the slope value is less than zero. Using a slope value greater than zero increases accuracy of the slope value when a loop count value of the loop of instructions in one iteration is greater than another loop count value of the loop of instructions in a preceding iteration. Using a slope value less than zero increases accuracy of the slope value when a loop count value of the loop of instructions in one iteration is less than another loop count value of the loop of instructions in a following iteration.

In another implementation form of the first and second aspects, the processing circuitry for executing the loop of instructions is at least part of other processing circuitry adapted for executing a set of instructions comprising a plurality of loops of instructions comprising the loop of instructions. Using the processing circuitry for executing the loop of instructions in other processing circuitry increases accuracy of an output of the other processing circuitry when executing the set of instructions.

Other systems, methods, features, and advantages of the present disclosure will be or become apparent to one with skill in the art upon examination of the following drawings and detailed description. It is intended that all such additional systems, methods, features, and advantages be included within this description, be within the scope of the present disclosure, and be protected by the accompanying claims.

Unless otherwise defined, all technical and/or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments. Although methods and materials similar or equivalent to those described herein can be used in the practice or testing of embodiments, exemplary methods and/or materials are described below. In case of conflict, the patent specification, including definitions, will control. In addition, the materials, methods, and examples are illustrative only and are not intended to be necessarily limiting.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) Some embodiments are herein described, by way of example only, with reference to the accompanying drawings. With specific reference now to the drawings in detail, it is stressed that the particulars shown are by way of example and for purposes of illustrative discussion of embodiments. In this regard, the description taken with the drawings makes apparent to those skilled in the art how embodiments may be practiced.

In the drawings:

FIG. 1 is a schematic block diagram of an exemplary processing circuitry, according to some embodiments;

FIG. 2 is a flowchart schematically representing an optional flow of operations, according to some embodiments;

FIG. 3 is a flowchart schematically representing another optional flow of operations, according to some embodiments;

FIG. 4A is an exemplary sequence of instructions comprising a plurality of loops of instructions; and

FIG. 4B is a table showing exemplary amounts of missed branch predictions, according to some embodiments.

DETAILED DESCRIPTION

Some embodiments described in the present disclosure relate to a processing circuitry and, more specifically, but not exclusively, to a processing circuitry for executing a loop of instructions.

For simplicity, the present disclosure discusses a branch having a structure of: if condition A is fulfilled then execute B, otherwise execute C.

When a loop of instructions has a loop count, i.e. an amount of times the loop of instructions should be executed, control of an instruction loop can be viewed in such a structure: before or after executing the instruction loop, check: if the loop needs to be executed another time then execute the first instruction of the loop of instructions, otherwise execute a consecutive instruction following the loop of instructions.

In some solutions at least part of both paths of a conditional branch are computed in parallel without actually altering a state of the processing unit. The state of the processing unit is altered only after the one or more conditions are computed. This is known also as speculative processing. In such solutions, a result of executing at least part of one path is discarded, without contributing to a result of executing the computer program. In such solutions, the processing unit has computing resources, for example processing circuitry, to execute at least part of each of two paths, increasing cost of manufacturing the processing unit. In addition, executing at least part of both parts increases an amount of power consumed by the processing unit, increasing cost of operation.

To reduce cost of operation and reduce cost of manufacturing the processing unit, some processing units comprise a branch predictor. As used in the present disclosure, the term branch predictor is used to mean processing circuitry for predicting whether a conditional branch instruction is taken or not before definitively computing the one or more conditions of the conditional branch instruction. Branch prediction may comprise predicting whether the one or more conditions are fulfilled or not. Without branch prediction, the processing unit may have to wait until the conditional branch instruction has passed an execute stage before a next instruction enters a fetch stage of the instruction pipeline. Waiting until the conditional branch instruction has passed the execute stage reduces throughput of the processing unit. Predicting whether the conditional branch instruction is more likely to be taken or not taken facilitates avoiding this waiting and increases throughput of the processing unit without computing both paths in parallel. In solutions with a branch predictor, the instruction that is predicted to be most likely is fetched and executed speculatively.

There exist solutions where for at least one conditional branch instruction, a record is kept whether the branch was taken or not. When a conditional branch instruction is executed more than once, a prediction whether the conditional branch instruction will be taken or not may be made according to one or more historical results of executing the conditional branch instruction. When the one or more conditions of the conditional branch instruction are regular, that is the one or more conditions do not change between one execution of the branch instruction and another execution of the branch instruction, a branch prediction computed using historical predictions may be sufficiently accurate. For example, when a loop of instructions is executed in a plurality of loop iterations, a conditional branch instruction controlling the loop may be taken for all of the plurality of loop iterations except for the last loop iteration, thus predicting the branch will be taken based on a history of taking the branch will be correct in all iterations except one.

A conditional branch instruction that controls execution of a loop of instructions is best predicted with a loop branch predictor that uses an amount of loop iterations in the plurality of loop iterations, known as a loop count value. A conditional branch condition that is executed many times one way and once another way may be identified as having loop behavior. In some solutions a branch predictor detects whether a conditional branch operation has loop behavior in addition to predicting whether the conditional branch operation is taken or not.

When a loop is executed a plurality of times, i.e. in a plurality of iterations, in each of the plurality of iterations the loop of instructions is executed an amount of times for that iteration. An amount of loop iterations the loop of instructions is executed in one of the plurality of iterations is henceforth referred to as a loop count value.

When a conditional branch operation is identified as having loop behavior, branch prediction may be made using a predicted loop count value, for example by comparing a current execution count value of the conditional branch instruction, known as an iteration count value, with the predicted loop count value. The predicted loop count value for a conditional branch operation may be predicted from historical executions of the loop of instructions.

However, when the one or more conditions are not regular, a likelihood of a branch prediction failing, that is predicting the wrong instruction, increases. For example, when a loop of instructions is executed a first time with one loop count value a predicted loop count value may be detected from executing the loop of instructions the first time. However, when executing the loop of instructions a second time with another loop count value, different from one first count value, using such a predicted loop count value branch prediction when executing the loop of instructions the second time may lead to an increase in false branch predichons for the conditional branch instruction controlling execution of the loop of instructions. One example of a non-regular loop count is a nest of loops where in each iteration of executing an outer loop, a loop count of a nested loop is an iteration count of the outer loop, thus incrementing or decrementing sequentially between iterations of the outer loop. A known algorithm comprising nested loops with non-regular loop counts is a Cholesky Factorization algorithm which computes a triangular matrix. In the triangular matrix each row of the matrix has an additional element compared to a previous row and therefore an amount of loop iterations is incremented sequentially.

To improve accuracy of a loop branch predictor in processing circuitry for executing a loop of instructions, the present disclosure proposes, in some embodiments described herein, computing an address of a predicted next instruction by using, in each iteration of a plurality of iterations, a slope value indicative of an expected change in a predicted loop count value when executing the loop of instructions in another of the plurality of iterations. Optionally the predicted next instruction address is provided to one or more parts of the processing circuitry for the purpose of retrieving a next instruction to execute. Optionally, when a prediction of the loop branch predictor is correct, executing the next instruction to execute modifies one or more states of the processing unit. Optionally, when the prediction is incorrect, executing the next instruction does not modify the one or more states of the processing unit. Optionally, when the prediction is incorrect, the processing unit is stalled until a correct instruction is retrieved. Optionally, when a loop of instructions is executed a plurality of times in each of a plurality of iterations, a predicted loop count value used in one of the plurality of iterations may be different from another predicted loop count value used in another of the plurality of iterations, increasing likelihood of predicting a correct next instruction address. Using a slope value indicative of an expected change in a predicted loop count value when executing the loop of instructions in another of the plurality of iterations increases a likelihood that another predicted loop count value used in the other iteration is equal to the other loop count value of the other iteration, thus increasing likelihood of predicting a correct next instruction address, and therefore reducing an amount of instructions instructed without impacting a state of the processing unit, thereby reducing cost of operation of the processing unit. In addition, when execution of a processing unit is stalled when the prediction is incorrect, as using the slope value increases the likelihood of predicting a correct next instruction address, using the slope value reduces an amount of time the processing unit is stalled, increasing throughput of the processing unit.

Optionally, an amount of processing circuitry resources required to implement a loop branch predictor that operates as described above is less than another amount of other processing circuitry resources required to implement parallel processing of instructions of more than one possible branch path. One example of a processing circuitry resource is an area of an electronic circuit formed on a semiconducting material. Another example of a processing circuitry resource is an amount of gates used in a field-programmable gate array component (FPGA). Thus, using a loop branch predictor as described above facilitates increasing throughput of the processing circuitry with a lower cost of implementation than implementing parallel processing of more than one possible branch path.

Optionally, the processing circuitry is configured for executing a plurality of instructions comprising a loop initialization instruction. Optionally, the slope value is an argument of the loop initialization instruction. In a non-limiting example, a first loop of instructions is controlled using a first iteration index initialized with a first initial value and modified until reaching a first count value. In this example, executing the first loop of instructions comprises executing in each of a plurality of iterations a second loop of instructions, controlled using a second iteration index initialized with a second initial value and modified until reaching the respective first iteration index value of the iteration. Thus, a loop initialization instruction initializing execution of the second loop of instructions may comprise a slope value greater than zero when the first iteration index is incremented between iterations (and therefore a loop count value of the second loop of instructions increases between iteration). Optionally, the loop initialization instruction initializing execution of the second loop of instructions comprises a slope value less than zero when the first iteration index is decremented between iterations (and therefore a loop count value of the second loop of instructions decreases between iteration). Optionally, the processing circuitry computes a slope value according to historical changes in a loop count value detected when executing the second loop of instructions in more than one iteration of the plurality of iterations.

Before explaining at least one embodiment in detail, it is to be understood that embodiments are not necessarily limited in its application to the details of construction and the arrangement of the components and/or methods set forth in the following description and/or illustrated in the drawings and/or the Examples. Implementations described herein are capable of other embodiments or of being practiced or carried out in various ways.

Embodiments may be a system, a method, and/or a computer program product. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the embodiments.

The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

Computer readable program instructions described herein can be downloaded to respective computing/processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and/or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. A network adapter card or network interface in each computing/processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing/processing device.

Computer readable program instructions for carrying out operations of embodiments may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of embodiments.

Aspects of embodiments are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer readable program instructions.

These computer readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

Reference is now made to FIG. 1, showing a schematic block diagram of an exemplary processing circuitry 100, according to some embodiments. In such embodiments, processing circuitry 100 comprises predictor 140, optionally for predicting an address of a next instruction. Optionally, processing circuitry 100 comprises a current instruction address 110. Optionally, current instruction address 110 is an address of a current executed instruction. Optionally, processing circuitry 100 is at least part of other processing circuitry, for example a processing unit. Optionally, the other processing circuitry is adapted for executing a set of instructions comprising a plurality of loops of instructions. Optionally, processing circuitry 100 is adapted for executing a loop of instructions, optionally the loop of instructions is one of the plurality of loops of instructions. Optionally, the loop of instructions comprises a start instruction. Optionally, the loop of instructions comprises an end instruction. Optionally, the loop of instructions comprises a branch point instruction and a predicted loop count value. Optionally the branch point instruction is the start instruction of the loop of instructions. Optionally the branch point instruction is the end instruction of the loop of instructions. Optionally, processing circuitry 100 comprises branch address 124, optionally for storing a branch address of the branch point instruction, for example an end instruction address of the end instruction of the loop of instructions or a start instruction address of the start instruction of the loop or instructions. Optionally, processing circuitry 100 comprises target instruction address 123, optionally for storing a target address of the branch point instruction, for example the start instruction address of the start instruction of the loop of instructions. Optionally, the branch address is the end instruction address of the end instruction of the loop of instructions. Optionally, processing circuitry 100 comprises predicted loop count value 121, optionally for storing the predicted loop count value of the loop of instructions. Optionally, processing circuitry 100 comprises current iteration count value 125, optionally for storing a current iteration count value when executing the loop of instructions. Optionally, processing circuitry 100 comprises slope value 122, optionally for storing a slope value used by predictor 140 when predicting a next instruction address.

Optionally, predictor 140 is connected to one or more of predicted loop count value 121, slope value 122, target instruction address 123, branch address 124, and current iteration count value 125. Optionally, predictor 140 is connected to current instruction address 110.

Optionally, processing circuitry 100 comprises a branch prediction table 130, optionally comprising a plurality of loop prediction entries. Optionally, each of the loop prediction entries describes one of a plurality of loops of instructions executed by the processing circuitry. Optionally, the plurality of loops of instructions executed by the processing circuitry are at least part of the plurality of loops of instructions the other processing circuitry is adapted for executing. Optionally, one or more of predicted loop count value 121, slope value 122, target instruction address 123, branch address 124, and current iteration count value 125 are members of one of the loop prediction entries of branch prediction table 130.

Optionally, processing circuitry 100 comprises at least one part 150 for retrieving a next instruction to execute. Optionally, at least one part 150 is connected to predictor 140. Optionally, at least one part 150 retrieves the next instruction to execute according to an output of predictor 140. Optionally, processing circuitry 100 comprises at least one other part 160 for computing one or more slope values. Optionally, at least one of the one or more slope values is computed according to one or more values of the plurality of loop prediction entries of branch prediction table 130. For example, at least one of the one or more slope values may be computed according to a plurality of predicted loop count values of the plurality of loop prediction entries of branch prediction table 130.

Optionally processing circuitry 100 executes the loop of instructions in each of a plurality of iterations. To do so, in some embodiments processing circuitry implements the following optional method.

Reference is now made also to FIG. 2, showing a flowchart schematically representing an optional flow of operations 200, according to some embodiments. In such embodiments, in each of the plurality of iterations, in 201 processing circuitry 100 computes a predicted next instruction address, optionally by predictor 140. Optionally, processing circuitry 100 computes the predicted next instruction address using slope value 122. Optionally, slope value 122 is indicative of an expected change in predicted loop count value 121 when executing the loop of instructions in another of the plurality of instructions. Optionally, processing circuitry 100 is configured for executing a plurality of instructions comprising a loop initialization instruction. Optionally, executing the loop of instructions comprises executing the loop initialization instruction. Optionally, the loop initialization instruction comprises a slope value argument. Optionally, slope value 122 is the slope value argument of the loop initialization instruction.

Optionally, processing circuitry 100 computes the predicted next instruction address when current instruction address 110 equals branch address 124. Reference is now made also to FIG. 3, showing another optional flow of operations 300, according to some embodiments. In such embodiments, in 301 processing circuitry 100 determines whether current iteration count value 125 is less than predicted loop count value 121.

When current iteration count value 125 is less than predicted loop count value 121, in 311 processing circuitry 100 optionally increments current iteration count value 125, optionally by 1. In 312, processing circuitry 100 optionally selects target instruction address 123 as the predicted next instruction address. Optionally, target instruction address 123 is the start instruction address of the start instruction of the loop of instructions.

When current iteration count value 125 is not less than predicted loop count value 121, in 321 processing circuitry 100 optionally increments predicted loop count value 121 by slope value 122. Optionally, slope value 122 is greater than zero. Optionally, slope value 122 is less than zero. Optionally, slope value 122 is equal zero. Optionally, in 322 processing circuitry 100 selects an instruction address consecutive to current instruction address 110 as the predicted next instruction address. Optionally, an absolute value of a difference between current instruction address 110 and the instruction address consecutive thereto is equal a size of the current executed instruction.

Optionally, flow of operations 300 is implemented by predictor 140.

Reference is now made again to FIG. 2. In 210, processing circuitry optionally provides the predicted next instruction address to at least one part 150, optionally for the purpose of retrieving a next instruction to execute.

EXAMPLES

The following example demonstrates improved correct branch predictions (known as hit predictions) of the circuitry and method described above, compared to other known in the art methods.

Reference is now made also to FIG. 4A, showing an exemplary sequence of instructions 400 for Cholesky Factorization, according to some embodiments. In this example, Cholesky Factorization is performed on a matrix having 32 rows and 32 columns. In this example, row 401 comprises a first loop branch point for a first loop using an index denoted by j, and row 402 comprises a second loop branch point for a second loop using an index denoted by k. The second loop is executed in each iteration of the first loop. In each iteration of the first loop, an amount of times the second loop is executed is equal to an iteration count value of the first loop.

Reference is now made also to FIG. 4B, showing table 410 showing exemplary amounts of missed branch predictions, according to some embodiments. Using some methods known in the art, an amount of missed predictions for j in line 401 is 31, as seen in 411. 412 shows that an amount of missed predictions for k in line 402 is 496 when using some methods known in the art. Thus, a total amount of missed predictions when executing sequence of instructions 400 using some methods known in the art is equal 527.

413 shows that another amount of missed predictions for j in line 401 is 0 when using circuitry and methods as described above. 414 shows that another amount of missed predictions for k in line 402 is 31 when using circuitry and methods as described above. Thus, another total amount of missed predictions when executing sequence of instructions 400 is equal 31 when using circuitry and methods as described above, that is only one seventeenth of the total amount of missed predictions when executing sequence of instructions 400 using some methods known in the art. Each missed prediction results in stalling processing by processing circuitry executing sequence of instructions 400, which reduces throughput of the processing circuitry. In this example the circuitry and method described above save 496 stall occasions, thus increasing throughput of the processing circuitry compared to using some other methods.

The descriptions of the various embodiments have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

It is expected that during the life of a patent maturing from this application many relevant processing circuitries will be developed and the scope of the term processing circuitry is intended to include all such new technologies a priori.

As used herein the term “about” refers to ± 10 %.

The terms "comprises", "comprising", "includes", "including", “having” and their conjugates mean "including but not limited to". This term encompasses the terms "consisting of and "consisting essentially of.

The phrase "consisting essentially of means that the composition or method may include additional ingredients and/or steps, but only if the additional ingredients and/or steps do not materially alter the basic and novel characteristics of the claimed composition or method.

As used herein, the singular form "a", "an" and "the" include plural references unless the context clearly dictates otherwise. For example, the term "a compound" or "at least one compound" may include a plurality of compounds, including mixtures thereof.

The word “exemplary” is used herein to mean “serving as an example, instance or illustration”. Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments.

The word “optionally” is used herein to mean “is provided in some embodiments and not provided in other embodiments”. Any particular embodiment may include a plurality of “optional” features unless such features conflict.

Throughout this application, various embodiments may be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of embodiments. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6 This applies regardless of the breadth of the range.

Whenever a numerical range is indicated herein, it is meant to include any cited numeral (fractional or integral) within the indicated range. The phrases “ranging/ranges between” a first indicate number and a second indicate number and “ranging/ranges from” a first indicate number “to” a second indicate number are used herein interchangeably and are meant to include the first and second indicated numbers and all the fractional and integral numerals therebetween.

It is appreciated that certain features of embodiments, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of embodiments, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable subcombination or as suitable in any other described embodiment. Certain features described in the context of various embodiments are not to be considered essential features of those embodiments, unless the embodiment is inoperative without those elements.

Although embodiments have been described in conjunction with specific embodiments thereof, it is evident that many alternatives, modifications and variations will be apparent to those skilled in the art. Accordingly, it is intended to embrace all such alternatives, modifications and variations that fall within the spirit and broad scope of the appended claims.

All publications, patents and patent applications mentioned in this specification are herein incorporated in their entirety by reference into the specification, to the same extent as if each individual publication, patent or patent application was specifically and individually indicated to be incorporated herein by reference. In addition, citation or identification of any reference in this application shall not be construed as an admission that such reference is available as prior art to embodiments. To the extent that section headings are used, they should not be construed as necessarily limiting.