Title:
CLAMP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2021/166679
Kind Code:
A1
Abstract:
This clamp circuit comprises: a first MOS transistor; and a second MOS transistor that is connected in series to the first MOS transistor. The gate of the first MOS transistor is connected to the drain of the first MOS transistor. The gate of the second MOS transistor is connected to the drain of the second MOS transistor. The clamp circuit is configured such that the first MOS transistor and/or the second MOS transistor exhibits a substrate bias effect.
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Inventors:
YASUSAKA MAKOTO (JP)
Application Number:
PCT/JP2021/004310
Publication Date:
August 26, 2021
Filing Date:
February 05, 2021
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H02H9/04
Foreign References:
| JP2013090278A | 2013-05-13 | |||
| JP2007014007A | 2007-01-18 |
Attorney, Agent or Firm:
SANO PATENT OFFICE (JP)
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