Title:
CLOCK DOMAIN CROSSING PROCESSING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2020/124566
Kind Code:
A1
Abstract:
The clock domain crossing processing circuit, configured to implement data processing between asynchronous clock domains with low latency. The clock domain crossing processing circuit comprises a jitter filter circuit and a synchronization circuit, wherein the jitter filter circuit is configured to perform jitter filter on a recovered input data clock, adjusting the clock phase after the jitter filter, and outputting the clock as an output data clock to the synchronization circuit, the synchronization circuit being configured to synchronize the input data across clock domains according to the input data clock and the output data clock. By performing jitter filter and phase-aligning on the input data clock, the input data clock can synchronize input data with low latency, so that the time delay of the data passing through the clock domain crossing processing circuit is small.
Inventors:
BAI YUJING (CN)
LIU XUHUI (CN)
LIU XUHUI (CN)
Application Number:
PCT/CN2018/122713
Publication Date:
June 25, 2020
Filing Date:
December 21, 2018
Export Citation:
Assignee:
HUAWEI TECH CO LTD (CN)
International Classes:
H04L7/00
Foreign References:
| CN104158646A | 2014-11-19 | |||
| CN101136739A | 2008-03-05 | |||
| CN107678488A | 2018-02-09 | |||
| CN103944583A | 2014-07-23 | |||
| US20180054295A1 | 2018-02-22 |
Other References:
See also references of EP 3879746A4
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