CLOCK GENERATION CIRCUIT, EQUIDISTANT FOUR-PHASE SIGNAL GENERATION METHOD, AND MEMORY

WIPO Patent Application WO/2023/206656

A1

A clock generation circuit, an equidistant four-phase signal generation method, and a memory. The clock generation circuit comprises: a four-phase clock generation circuit (801), which is used for receiving an internal clock signal and a complementary clock signal of a memory to which the clock generation circuit belongs, and is configured to generate a first clock signal, a second clock signal, a third clock signal and a fourth clock signal which have the same period; a signal delay circuit (802), which is configured to respectively perform signal delay on the first clock signal, the second clock signal, the third clock signal and the fourth clock signal on the basis of a delay command, wherein delays between the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are different; a signal loading circuit (805), which is used for generating a first indication signal and a second indication signal; and a test circuit (400), which is used for performing duty cycle measurement on the basis of the first indication signal and the second indication signal, so as to acquire equidistant parallel clock signals.

QIN JIANYONG (CN)
LI JIANNI (CN)
LIU ZHONGLAI (CN)

PCT/CN2022/093711

November 02, 2023

May 19, 2022

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CHANGXIN MEMORY TECH INC (CN)

H03K5/15

CN111835349A	2020-10-27
CN114257235A	2022-03-29
CN113346739A	2021-09-03
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CN104753524A	2015-07-01
CN210899108U	2020-06-30
CN103840796A	2014-06-04
US20070223638A1	2007-09-27

SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)

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