CLAIM OF PRIORITY

[0001] The present application claims the benefit of priority of US patent application S/N: 13/707,748, entitled "CLOCK PHASE SHIFT DETECTOR", filed December 7, 2012, with the United States Patent and Trademark Office, the content of which is incorporated herein by reference in its entirety.

BACKGROUND a. Field of the Invention

[0002] The present invention generally relates to clock signals, and more particularly to maintaining the integrity of phase relationships between clock signals. b. Background of Invention

[0003] Clock signals may be used in, among other things, digital communications and digital systems in general. As the integrity of the clock signals deteriorate, so may the overall operation and/or performance of the system. Quadrature clocks may be used in many digital system applications such as high-speed digital transmitters and receivers. Quadrature clocks may typically include two clock signals having a phase separation or difference of 90° (π/2).

[0004] Clock skew problems may cause a departure in the 90° (π/2) phase relationship of quadrature clock signals, which in turn may impact the system performance of the device or system using these clock signals. For example, in high-speed communication applications where quadrature clock signals provide the requisite timing for signal transmission and reception, phase variations in quadrature clock signals may ultimately cause an increase in bit-error rate (BER).

[0005] Variations in process, voltage, and temperature (PVT) may contribute to causing clock skew within, for example, semiconductor devices that include quadrature clocks. In addition, unmatched clock paths within circuits may also contribute to increased clock skew problems. It may, therefore, be advantageous, among other things, to maintain requisite phase relationships between signals such as for example, quadrature clock signals. BRIEF SUMMARY

[0006] According to one exemplary embodiment, a clock phase shift detector circuit may include a phase detector that receives a first and a second clock signal, a current mirror, a first comparator, and a second comparator. The phase detector generates a phase signal based on a phase difference between the first and the second clock signal. The current mirror is coupled to the phase detector and includes a first integrator, a second integrator, and a third integrator, such that the first integrator integrates the first clock signal and generates a first voltage, the second integrator integrates the first clock signal and generates a second voltage, and the third integrator integrates the phase signal and generates a third voltage. The first comparator is coupled to the first and the third integrator, whereby the first comparator receives the first and the third voltage. The first comparator generates a first control signal based on an amplitude comparison between the first and the third voltage. The second comparator is coupled to the second and the third integrator, whereby the second comparator receives the second and the third voltage. The second comparator generates a second control signal based on an amplitude comparison between the second and the third voltage. The generated first and second control signal detect a change between the phase difference of the first and the second clock signal and an optimized phase difference.

[0007] According to another exemplary embodiment, a method of detecting a shift in phase relationship between a first and a second clock signal may include determining a phase difference between the first and the second clock signal, and integrating the first clock signal for generating a first voltage value. The first clock signal is also integrated for generating a second voltage value. The determined phase difference is integrated for generating a third voltage value. The first and the third voltage value are then compared for generating a first control signal. Also, the second and the third voltage value are compared for generating a second control signal, whereby the first and the second control signal detect the phase relationship between the first and the second clock signal. Based on the third voltage value being between the first and the second voltage value, the first and the second control signal detect no adjustment requirement for the determined phase difference between the first and the second clock signal. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0008] FIGS. 1A and IB illustrate a clock phase shift detector (PSD) unit according to an exemplary embodiment;

[0009] FIG. 2 is an operational flow chart corresponding to the exemplary embodiment of the PSD unit shown in FIGS. 1A and IB; and

[0010] FIG. 3 is a clock phase control circuit that utilizes the exemplary PSD embodiment depicted in FIGS. 1A-1B.

[0011] The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements.

DETAILED DESCRIPTION

[0012] The following one or more exemplary embodiments describe a clock phase shift detector (PSD) unit that detects any phase deviation between two input clock signals based on a predetermined phase relationship. For example, in one implementation, a 90° or π/2

predetermined phase relationship may be required for two clock signals operating within a device or circuit. Accordingly, the following described PSD unit receives the two clock signals and detects any phase deviation or change in the 90° or π/2 phase relationship between the clocks. It may be appreciated, however, that the PSD unit may be utilized for detecting a phase deviation of an alternative predetermined value (e.g., 75°) between the two input clock signals.

[0013] Referring to FIGS. 1A and IB, a clock phase shift detector (PSD) unit 100 according to an exemplary embodiment is illustrated. The PSD unit 100 may include a phase detector 102 (FIG. 1A); a current mirror circuit 104 (FIG. 1A), and voltage comparator devices 106 (FIG. IB) and 108 (FIG. IB). Any known voltage comparator or phase detector device may be used for implementing the PSD unit 100. For example, as depicted, the phase detector 102 may be implemented by a NAND gate device. Alternative, the phase detector 102 may include an XOR or AND gate device (not shown). The clock phase shift detector (PSD) unit 100 receives a first clock signal / and a second clock signal Q, and generates an output VI, V2 that is indicative of, or detects, whether the phase difference between the / and Q clock signals has deviated from a predetermined desired value (i.e., an optimized phase difference of 90° or π/2).

[0014] Referring to FIG. 1A, current mirror 104 includes a primary current path 110. The current flowing in primary current path 110 is mirrored in secondary current paths 112a, 112b, and 112c. Current path 112a may include pFET transistor device Pi, pFET transistor device P ₄ , nFET reset control transistor Ni, and capacitor device Ci. The pFET transistor device Pi sources the current that flows within current path 112a. The pFET transistor device P ₄ receives the first clock signal / at its gate 114, whereby the pFET transistor device P ₄ is switched ON and OFF as the voltage levels of first clock signal / switch between, for example, ground (e.g., Ov) and the supply voltage (e.g., Vdd). In particular, pFET transistor device P ₄ is switched OFF during the positive pulse period (i.e., Vdd) of clock / and switched ON during periods of the clock signal / that are at about Ov or ground. When pFET transistor device P ₄ is switched ON, the current sourced by pFET transistor device Pi flows through pFET transistor device P ₄ and charges capacitor Ci. Thus, the capacitor Ci integrates this current flow to generate a voltage signal Vci at terminal Ti of the capacitor Ci. In affect, since the clock signal / controls the current flow and subsequent integration process at capacitor Ci, the voltage signal Vci may correspond to an integrated version of clock signal /. Following each integration measurement, a positive reset pulse may be applied to the gate 125a of nFET reset control transistor Ni in order to discharge capacitor Ci prior to the next integration measurement. If the capacitor Ci is not discharged, the capacitor Ci will continue to ramp up and remain at the supply voltage value (e.g., Vdd).

[0015] Current path 112b may include pFET transistor device P ₂ , pFET transistor device P5, nFET reset control transistor N ₂ , and capacitor device C ₂ . The pFET transistor device P ₂ sources the current that flows within current path 112b. The pFET transistor device P5 also receives clock signal / at its gate 116, whereby the pFET transistor device P5 is switched ON and OFF as the voltage levels of first clock signal / switch between, for example, ground (e.g., Ov) and the supply voltage (e.g., Vdd). In particular, pFET transistor device P5 is switched OFF during the positive pulse period (i.e., Vdd) of clock / and switched ON during periods of the clock signal / that are at about Ov or ground. When pFET transistor device P5 is switched ON, the current sourced by pFET transistor device P ₂ flows through pFET transistor device P5 and charges capacitor C ₂ . Thus, the capacitor C ₂ integrates the current flow to generate a voltage signal Vc ₂ at terminal T ₂ of the capacitor C ₂ . In affect, since the clock signal / controls the current flow and subsequent integration process at capacitor C ₂ , the voltage signal Vc ₂ may correspond to an alternative integrated version of clock signal /. Following each integration measurement, a positive reset pulse may be applied to the gate 125b of nFET reset control transistor N ₂ in order to discharge capacitor C ₂ prior to the next integration measurement. If the capacitor C ₂ is not discharged, the capacitor C ₂ will continue to ramp up and remain at the supply voltage value (e.g., Vdd).

[0016] The phase detector 102 receives the first clock signal / and the second clock signal Q at inputs 120 and 122, respectively. The phase detector 102 then generates a phase signal at its output 124 (Z) based on the phase relationship between the first clock signal / and the second clock signal Q at it inputs 120, 122. Since the exemplary phase detector 102 may be

implemented using a NAND gate circuit, only overlapping portions of the / and Q clocks both having a logic-high voltage level (e.g., Vdd) will generate a logic 0 (e.g., GND or Ov) at output 124. All other combinations of voltage levels (i.e., different voltage levels or both at Ov) corresponding to the clocks /, Q will cause a logic 1 (e.g., Vdd) at output 124. Thus, the generated phase signal' s Ov pulse periods may be used to indicate the measure of phase difference between the / and Q clocks. For example, when the phase relationship between the / and Q clocks is about 90° or π/2, the generated phase signal's Ov pulse period may be a value that is about one quarter (1/4) of the pulse period of either the / or the Q clock. As the phase relationship between the / and Q clocks exceeds 90° or π/2, the generated phase signal' s Ov pulse duration value becomes less one quarter (1/4) of the pulse period of either the / or the Q clock. Alternatively, as the phase relationship between the / and Q clocks becomes less than 90° or π/2, the generated phase signal's Ov pulse duration value becomes more than one quarter (1/4) of the pulse period of either the / or the Q clock. As described in the following, these fluctuations in the phase signal may be used to detect any phase deviations from an optimized phase difference.

[0017] Current path 112c may include pFET transistor device P ₃ , pFET transistor device P^, nFET reset control transistor N3, and capacitor device C ₃ . The pFET transistor device P ₃ sources the current that flows within current path 112c. The pFET transistor device Pe receives the phase signal Z from output 124 of the phase detector at its gate 118, whereby the pFET transistor device P^ is switched ON and OFF as the voltage levels of phase signal Z switch between, for example, ground (e.g., Ov) and the supply voltage (e.g., Vdd). In particular, pFET transistor device Pe is switched OFF during the positive pulse duration (i.e., Vdd) of phase signal Z and switched ON during durations of the phase signal Z that are at about Ov or ground. When pFET transistor device P^ is switched ON, the current sourced by pFET transistor device P ₃ flows through pFET transistor device P^ and charges capacitor C ₃ . Thus, the capacitor C ₃ integrates the current flow to generate a voltage signal Vc ₃ at terminal T3 of the capacitor C ₃ . In affect, since the phase signal Z controls the current flow and subsequent integration process at capacitor C ₃ , the voltage signal Vc ₃ may correspond to an integrated version of phase signal Z. Following each integration measurement, a positive reset pulse may be applied to the gate 125c of nFET reset control transistor N3 in order to discharge capacitor C ₃ prior to the next integration measurement. If the capacitor C ₃ is not discharged, the capacitor C ₃ will continue to ramp up and remain at the supply voltage value (e.g., Vdd).

[0018] In current path 112a, capacitor Ci acts as a first integrator that integrates the / clock signal and generates reference voltage Vci- In current path 112b, capacitor C ₂ acts as a second integrator that also integrates the / clock signal and generates reference voltage Vc ₂ . Reference voltage Vci is always greater than Vc ₂ based on the difference in channel width (i.e. Wi vs. W ₂ ) between pFET transistor devices Pi and P ₂ , respectively. Thus, the reference voltages Vci, Vc ₂ provide a voltage reference window having an upper limit determined by the value of Vci and a lower limit determined by the value of Vc ₂ . If the integrated phase signal, which generates voltage Vc ₃ , lies within the voltage reference window, it may be indicative that no phase adjustment is necessary. [0019] In essence, the voltage reference window acts as a tolerance window or tolerance voltage range over which no corrective phase control may be necessary. By having such a tolerance window or tolerance voltage range, the output VI, V2 of the PSD unit 100 is not constantly detecting and signalling phase corrective measures. This in turn minimizes the jitter that may be observed in the phase relationship of the clock signals /, Q as a result of constant phase adjustments by the comparator about a single reference point. For example, with a single reference voltage (e.g., Vi), a PSD unit comparator output may constantly toggle between Vdd and Ov (i.e., causing jitter) based on the phase signal being adjusted about the single reference voltage. In contrast, with the voltage reference window, the comparator outputs of PSD unit 100 may toggle between Vdd and Ov based only on the phase signal falling outside the voltage range of the voltage reference window.

[0020] As explained above, reference voltage Vci is always greater than Vc ₂ based on the difference in channel width (i.e. Wi vs. W ₂ ) between pFET transistor devices Pi and P ₂ , respectively. As depicted in FIG. 1A, the channel width of pFET transistor device Pi is given by Wi=KWo+A W, where ^" is a constant and +AW is an added channel width. The channel width of pFET transistor device P ₂ on the other hand is given by W ₂ =KWo-AW, where ^" is a constant and -A W is a reduced channel width. Thus, since Wi is implemented to be larger than W ₂ , pFET transistor device Pi sources more current than pFET transistor device P ₂ and, therefore, voltage signal Vci is always greater than voltage signal Vc ₂ . This voltage difference between Vci and Vc ₂ provides the reference voltage window. It may be appreciated that the currents sourced in current paths 112a and 112b depend mainly on the channel widths Wi, W ₂ due to both pFET transistor devices Pi and P ₂ being driven by the same input signal (i.e., / clock) and pFET transistor devices P ₄ and P5 being identical.

[0021] The pFET transistor device Ps has a channel width given by W ₃ =2KWo, where A is a constant. The channel width of the pFET transistor device P3 is designated to be approximately twice the size of the channel widths Wi, W ₂ of pFET transistor devices Pi and P ₂ . This increase in channel width (W3) is due to the phase signal Z driving pFET transistor device having a narrower pulse duration compared to that of the / clock signals driving pFET transistor devices P ₄ and P5. When the phase relationship between the / and Q clock signals is approximately optimized at 90° or π/2, the width of the phase signal Z pulse period may be approximate half that of the I clock signal. Thus, in order to compensate for the narrower pulse duration (signal Z) received at pFET transistor device P^, the width W3 of pFET transistor device P3 is

approximately doubled in order to source more current during the smaller pulse duration. This in turn causes enough current to flow along path 112c so that the generated voltage signal Vc ₃ (i.e., integrated phase signal Z) falls within the voltage range of the voltage reference window set by Vci and Vc ₂ . In the depicted embodiment of current mirror 104, pFET transistor devices P4-P6 are identical. Also, capacitor devices C1-C ₃ are identical.

[0022] Referring to FIG. IB, the voltage comparators 106, 108 receive the integrated first clock signal defined by voltage signal Vci, the integrated first clock signal defined by voltage signal Vc ₂ , and the integrated phase signal defined by voltage signal Vc ₃ - Specifically, voltage comparator 106 receives the integrated first clock signal defined by voltage signal Vci and the integrated phase signal defined by voltage signal Vc ₃ - Voltage comparator 108 receives the other integrated first clock signal defined by voltage signal Vc ₂ and the integrated phase signal defined by voltage signal Vc ₃ - The voltage levels of the integrated first clock signals and the integrated phase signal are then compared by voltage comparators 106 and 108. Depending on which voltage is greater, the comparator outputs Vi, V ₂ swing to either their supply voltage (Vdd or logic 1) or ground (GND or logic 0). It may be appreciated that the generated phase signal described in the following may be based on NAND gate phase detector. As previously indicated, AND, XOR, or any other phase detector circuit may be used in association with voltage comparators 106 and 108. However, different phase detector circuits may contribute to generating different comparator output Vi, V ₂ signals and, therefore, a phase control circuit (e.g., FIG. 3: phase delay stage 302) may provide phase control in accordance with the particular comparator output Vj, V ₂ signals received.

[0023] As indicated by scenario 130, for example, the integrated phase signal defined by voltage signal Vc ₃ may be larger than both the integrated first clock signal defined by voltage signal Vci and the integrated first clock signal defined by voltage signal Vc ₂ . When the phase difference between the clock signals /, Q are less than the optimized 90° or π/2 value, the generated pulse (logic l→logic 0 transition) at the output 124 (FIG. 1A) of the phase detector 102 (FIG. 1A) may have an increased pulse width. This increased pulse width switches pFET transistor device P ON for a longer duration, which raises voltage signal Vc ₃ above Vci and Vc ₂ . Thus, at comparator 106, since Vc ₃ is greater than Vci, the output Vj of comparator 106 is at Ov or logic 0. At comparator 108, since Vc ₃ is also greater than Vc ₂ , the output V ₂ of comparator 108 is also at Ov or logic 0. Accordingly, the Ov or logic 0 values of Vi and V ₂ may be used as a control signal to adjust the phase of one of the clocks towards achieving the optimized phase difference of about 90° or π/2. This may be accomplished by, for example, delaying one of the clocks (/) in order to increase the phase difference between the clocks /, Q.

[0024] As indicated by scenario 140, for example, the integrated phase signal defined by voltage signal Vc ₃ may be less than both the integrated first clock signal defined by voltage signal Vci and the integrated first clock signal defined by voltage signal Vc ₂ . When the phase difference between the clock signals /, Q is greater than the optimized 90° or π/2 value, the generated pulse (logic l→logic 0 transition) at the output 124 (FIG. 1A) of the phase detector 102 (FIG. 1A) may have a reduced pulse width. This reduced pulse width switches pFET transistor device Pe ON for a shorter duration, which reduces voltage signal Vc ₃ below both Vci and Vc ₂ . Thus, at comparator 106, since Vc ₃ is less than Vci, the output Vj of comparator 106 is at Vdd (i.e., supply voltage) or logic 1. At comparator 108, since Vc ₃ is also less than Vc ₂ , the output V ₂ of comparator 108 is also at Vdd (i.e., supply voltage) or logic 1. Accordingly, the Vdd values of Vi and V ₂ may be used as a control signal to adjust the phase of one of the clocks towards achieving the optimized phase difference of about 90° or π/2. This may be accomplished by, for example, delaying one of the other clocks (/) in order to reduce the phase difference between the clocks /, Q.

[0025] As indicated by scenario 150, for example, the integrated phase signal defined by voltage signal Vc ₃ may be between the integrated first clock signal defined by voltage signal Vci and the integrated first clock signal defined by voltage signal Vc ₂ . Under these conditions, the integrated phase signal defined by voltage signal Vc ₃ lies within the voltage reference window determined by the Vci and Vc ₂ values. When the phase difference between the clock signals /, Q are approximately optimized at 90° or π/2, the generated pulse (logic l→logic 0 transition) at the output 124 (FIG. 1A) of the phase detector 102 (FIG. 1A) may have a pulse width that switches the pFET transistor device P ON for a duration that raises voltage signal Vc ₃ to be within Vci and Vc ₂ . Thus, at comparator 106, since Vc ₃ is less than Vci, the output Vi of comparator 106 is at Vdd (i.e., supply voltage) or logic 1. At comparator 108, since Vc ₃ is greater than Vc ₂ , the output V ₂ of comparator 108 is at Ox or logic 0. Accordingly, the Vj and V ₂ values of Vdd (logic 1) and Ox (logic 0), respectively, may be used as a control signal that is indicative that no phase adjustment of the clocks /, Q towards achieving the optimized phase difference of about 90° or π/2 is necessary.

[0026] An optimized phase difference between the clock signals may include any predetermined or selected target phase difference. For example, if a system or device requirement is a clock pair having a 90° or π/2 phase difference, then this phase difference (90° or π/2) value becomes the optimized phase difference, which is to be maintained. Alternatively, for example, in other implementations a system or device requirement may include a clock pair having a 45° or π/4 phase difference. In such an example, the optimized phase difference becomes the target 45° or π/4 phase difference.

[0027] FIG. 2 is an operational flow chart 200 corresponding to the exemplary embodiment of the PSD unit shown in FIGS. 1A and IB. The flow chart will be described with the aid of the PSU unit 100 depicted in FIGS. 1A and IB. At 202, the integrators, which include capacitors C ₁ -C ₃ , are reset by applying a positive pulse to the nFET reset control transistor N ₁ -N3. This may cause the stored voltage across the capacitors to be discharged as the nFET reset control transistors N ₁ -N3 electrically couple or short the terminals of each of the respective

capacitors C ₁ -C ₃ .

[0028] At 204, the integrated voltage signals Vci, Vc ₂ , Vc ₃ at each current path 112a-112c are generated over pre-defined / clock cycles. For example, at path 112a, current flowing through pFET devices Pi and P4 under the control the / clock signal (i.e., negative pulse period) is integrated to generate voltage Vci- Also, at path 112b, current flowing through pFET devices P ₂ and P5 under the control the / clock signal (i.e., negative pulse period) is integrated to generate voltage Vc ₂ . Further, at path 112c, current flowing through pFET devices P3 and under the control the phase signal Z (i.e., negative pulse period) generated at the output 124 of the phase detector 102 is integrated to generate voltage Vc ₃ -

[0029] At 206, it may be determined whether generated voltage Vc ₃ is greater than generated voltages Vci and Vc ₂ . If not, the process moves to 214. If so, at 208 it may be detected that the / and Q clock signals have a phase difference that is less than the optimized phase difference of, for example, 90° or π/2. Accordingly, at 210 both comparator 106 (CMP1) and comparator 108 (CMP2) generate a logic 0. At 212, the comparator outputs (i.e., Vi=0, V ₂ =0) may be used as control signals to delay, for example, the Q clock signal in order to increase the relative phase difference between the clock signals /, Q. By increasing the Q clock delay, the phase difference between the clock signals /, Q may approach the desired optimized phase difference value (e.g., 90° 0Γ π/2).

[0030] At 214, it may be determined whether generated voltage Vc ₃ is between generated voltages Vci and Vc ₂ . If not, the process moves to 222. If so, at 216 it may be detected that the / and Q clock signals have a phase difference that is approximately the same as the optimized phase difference of, for example, 90° or π/2. Accordingly, at 218 comparator 106 (CMP1) generates a logic 1 (i.e., Vi=l) and comparator 108 (CMP2) generate a logic 0 (i.e., V ₂ =0). At 220, the comparator outputs (i.e., Vi=l, V ₂ =0) may be used as control signals that are indicative that any phase difference adjustment between the clock signals /, Q is not necessary. Thus, when the value of generated voltage Vc ₃ is between the voltage tolerance window produced by voltages Vci and Vc ₂ , no phase difference adjustment between the clock signals /, Q may be needed.

[0031] At 222, it may be determined whether generated voltage Vc ₃ is less than generated voltages Vci and Vc ₂ . If so, at 224 it may be detected that the / and Q clock signals have a phase difference that is greater than the optimized phase difference of, for example, 90° or π/2.

Accordingly, at 226 both comparator 106 (CMP1) and comparator 108 (CMP2) generate a logic 1 (i.e., Vi=l, V ₂ =l). At 212, the comparator outputs (i.e., Vi=0, V ₂ =0) may be used as control signals to delay, for example, the / clock signal in order to decrease the relative phase difference between the clock signals /, Q. By increasing the / clock delay, the phase difference between the clock signals /, Q may approach the desired optimized phase difference value (e.g., 90° 0Γ π/2).

[0032] FIG. 3 is a clock phase control circuit 300 that may utilize the exemplary PSD

embodiment 100 depicted in FIGS. 1A and IB. As depicted, at the PSU 100, the outputs Vi, V ₂ of the comparators 106, 108 (FIG. 1) may generate control signals that are fed to a phase delay stage 302 in order to control the phase relationship between input clock signals / and Q. Based on the control signal voltages at outputs Vj and V ₂ , the phase delay stage 302 may apply a phase correction to one of the clock signals (e.g., clock Q) until the desired phase relationship between the clock signals /, Q is established.

[0033] As described in the above paragraphs, the clock inputs /, Q' to the PSU 100 are processed in order to detect their phase relationship. For example, based on the phase relationship between the clock inputs /, Q' being less than 90° or π/2, the control signals generated at the outputs Vj, V ₂ of the comparators 106, 108 may both be at logic 0. Applying these logic 0 control values to the phase delay stage 302 may signal the phase delay stage 302 to increase the delay of the input Q clock relative to the / clock and generate increased delay clock Q'. As the clock Q' is delayed and the / and Q' clocks approach the 90° or π/2 target phase difference, the voltage difference between the comparator inputs (FIG. 2: Vc ₃ , Vc ₂ , Vci) start to decrease until Vc ₃ lies within Vc ₂ and Vci, and, therefore, no more phase adjustment via delay stage 302 is necessary.

[0034] Alternatively, based on the phase relationship between the clock inputs /, Q' being more than 90° or π/2, the control signals generated at the outputs Vj, V ₂ of the comparators 106, 108 may both be at logic 1. Applying these logic 1 control values to the phase delay stage 302 may signal the phase delay stage 302 to decrease the delay of the input Q clock relative to the / clock and generate decreased delay clock Q'. As the clock Q' is delayed less and the / and Q' clocks approach the 90° or π/2 target phase difference, the voltage difference between the comparator inputs (FIG. 2: Vc ₃ , Vc ₂ , Vci) start to decrease until Vc ₃ once again lies within Vc ₂ and Vci, and, therefore, no more phase adjustment via delay stage 302 is necessary. [0035] Further, based on the phase relationship between the clock inputs /, Q' being approximately 90° or π/2, the control signal generated at the output Vi of comparator 106 may be at logic 1, while the control signal generated at the output V ₂ of comparator 108 may be at logic 0. Applying these logic 1 and logic 0 control values to the phase delay stage 302 may signal the phase delay stage 302 that no clock phase adjustment is necessary. As previously described, the generated Vc3 value may be between the generated Vc ₂ and Vci values without triggering any phase adjustment via the comparator outputs. Therefore, even though the phase difference between the clock signal may deviate slightly from the optimized value of 90° or π/2, the reference voltage window produced by the Vci and Vci values provide a phase difference tolerance range over which no adjustment between the / and Q' clocks is necessary.

Consequently, jitter associated with the comparator output and, therefore, jitter associated with phase difference between the clocks /, Q' clocks is mitigated.

[0036] The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the one or more

embodiment, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.