Title:
CLOSED-GRID BUS ARCHITECTURE FOR WAFER INTERCONNECT STRUCTURE
Document Type and Number:
WIPO Patent Application WO2002005606
Kind Code:
A3
Abstract:
An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate iso lated resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the water.
Inventors:
MILLER CHARLES A (US)
LONG JOHN M (US)
LONG JOHN M (US)
Application Number:
PCT/US2001/021196
Publication Date:
April 18, 2002
Filing Date:
July 02, 2001
Export Citation:
Assignee:
FORMFACTOR INC (US)
MILLER CHARLES A (US)
LONG JOHN M (US)
MILLER CHARLES A (US)
LONG JOHN M (US)
International Classes:
G01R1/073; H05K1/02; H05K1/00; (IPC1-7): G01R31/319; G01R1/073; H01L21/66
Foreign References:
| US5592632A | 1997-01-07 | |||
| DE3637502A1 | 1988-05-11 | |||
| US5086271A | 1992-02-04 | |||
| US4994735A | 1991-02-19 | |||
| US6047469A | 2000-04-11 |
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