Title:
COLUMNAR SEMICONDUCTOR DEVICE HAVING SGT, AND METHOD FOR MANUFACTURING SAME
Document Type and Number:
WIPO Patent Application WO/2016/163045
Kind Code:
A1
Abstract:
On a NiSi layer (28aa) of a lower wiring conductor layer connected to an N+ layer (31b) of a surrounding gate transistor (SGT), said N+ layer being formed in a Si column (6b), a first contact hole (40a) is formed, said first contact hole penetrating a NiSi layer (36a) of an upper wiring conductor layer connected to a gate TiN layer (18d), and a NiSi layer (28bb) of an intermediate wiring conductor layer connected to an N+ layer (33b). Then, on the NiSi layer (36a), a second contact hole (40c) surrounding the first contact hole in plan view is formed, an insulating SiO2 layer (41a) is formed on a side surface of the NiSi layer (28bb), and the NiSi layer (28bb) and the NiSi layer (36a) are connected to each other by means of a wiring metal layer (42b) via the contact holes (40a, 40c).
Inventors:
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2015/078776
Publication Date:
October 13, 2016
Filing Date:
October 09, 2015
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
MASUOKA FUJIO (JP)
HARADA NOZOMU (JP)
International Classes:
H01L21/8244; H01L27/11
Domestic Patent References:
| WO2014184933A1 | 2014-11-20 |
Foreign References:
| JP2012209340A | 2012-10-25 | |||
| JPH0324753A | 1991-02-01 |
Attorney, Agent or Firm:
KIMURA MITSURU (JP)
Mitsuru Kimura (JP)
Mitsuru Kimura (JP)
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