Field of the invention

The present invention relates to a combination of a local oscillator system and a sub-harmonic mixer for providing a down-conversion (or an up-conversion) scheme based on a sub-harmonic local oscillator. More in particular, the combination comprises an oscillating signal generator, and a quadrature phase generation unit based on an injection locking method connected to an output of the oscillating signal generator. Prior art

The article by Jianhua Lu, et al, "A Compact and Low Power 5-10 GHz Quadrature Local Oscillator for Cognitive Radio Applications," in IEEE Journal of Solid-State Circuits, VOL. 47, NO. 5, May 2012, discloses a quadrature local oscillator for radio applications. The design disclosed in this publication utilizes an injection locked ring oscillator to realize quadrature local oscillator phases of a divide-by-three divider. This however results amongst others in a high power consumption.

The article by Christopher A. De Vries, et al, "Subsampling Architecture for Low Power Receivers," in IEEE Transactions on Circuits and Systems-II: Express Briefs, VOL. 55, NO. 4, April, 2008, discloses a subsampling receiver requiring a lower frequency synthesizer. However, a high quality bandpass anti-aliasing filter is required to obtain a well functioning receiver design, increasing overall cost.

The article by Ahmed Musa et al., "A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM- Wave Applications", IEEE Journal of Solid- State Circuits, vol. 46 no. 1, pages 2635-2649, discloses a low phase noise quadrature injection locked frequency synthesizer. In a particular embodiment, a sub harmonic VCO and a super harmonic QILO is used to generate a quadrature 60 GHz LO signal.

International patent publication WO 2011/003040 discloses a local oscillator and frequency multiplying sub harmonically injection-locked oscillator (SHILO), which receives a low frequency signal and generates a higher frequency signal. The frequency of the relatively low frequency signal communicated from the local oscillator to the SHILO is lower than the frequency of the I and Q signals that drive a mixer.

The article by Sunghwan Kim et al. "A 44-GHz 8-element phased-array SiGe HBT transmitter RFIC with an injection- locked quadrature frequency multiplier", Radio Frequency Integrated Circuits Symposium (RFIC), 23 May 2010, pages 453-456, discloses a frequency doubling injection- locked quadrature oscillator, which can be used at each transmitter element to reduce power consumption and LO signal loss during distribution. The disclosed oscillator functions as a quadrature frequency doubler that generates differential quadrature outputs from a single differential signal input.

Summary of the invention

The present invention seeks to provide an improved local oscillator system having lower power requirements than prior art systems.

According to the present invention, a combination of a local oscillator system and a sub-harmonic mixer according to the preamble defined above is provided, further comprising and a sub-harmonic mixer connected to an output of the quadrature phase generation unit, wherein the oscillating signal generator and quadrature phase generation unit (and all the succeeding buffer stages) operate at a first frequency ( vco) which is a sub-harmonic of an operational frequency ( Lo), the operational frequency ( Lo) being only virtually present. It has to be noted that f _LO is a virtual signal which is not present at any stage of this particular combination, because the frequency doubling is an intrinsic feature of a subharmonic mixer. However, for discussion convenience (easier comparison with traditional local oscillator systems), we always define a signal with frequency of LO- It is noted that in this structure, the local oscillator system is dedicated to work together with the sub-harmonic mixer. Thus, only the final stage, i.e. the sub-harmonic mixer, is operating (partly) on the operational frequency / O, and consequently, the combination according to the present invention embodiments will be more power efficient.

In a further aspect, the present invention relates to an integrated circuit comprising a combination according to any one of the embodiments described herein, e.g. in the form of a receiver circuit, transmitter circuit or transceiver circuit. This allows a low cost on-chip implementation for a radio integrated circuit having low power requirements. Short description of drawings

The present invention will be discussed in more detail below, using a number of exemplary embodiments, with reference to the attached drawings, in which

Fig. la-d show prior art examples of local oscillator system architectures;

Fig. 2 shows a general diagram of an embodiment of the present invention subharmonic oscillator system;

Fig. 3 shows an embodiment of the subharmonic oscillator system using an injection locked ring oscillator (ILRO);

Fig. 4a and 4b show details of further embodiments, using an injection locked frequency doubler (ILFD) or injection locked frequency tripler (ILFT); and

Fig. 5 shows an embodiment of a part of the local oscillator system embodiment of Fig. 3 and the effect of an exemplary interference situation.

Detailed description of exemplary embodiments

In low power radios, the peak power consumption of a local oscillator (LO) system is of importance because:

(1) the LO system has to be activated in both transmitting and receiving modes;

(2) in duty-cycled radios, the receiver (Rx) together with the LO have to be activated frequently to listen to the channel;

(3) LO systems are supposed to have certain characteristics, e. g. having low phase noise, low spurs, generating quadrature or multiple phases, generating different signal duty cycles, having sufficient driving capability (enough output

power/amplitude), etc.; and

(4) to avoid a pulling issue, the oscillator frequency should be sufficiently different from the radio frequency (RF) frequency, which is normally realized by a high-frequency oscillator with a frequency divider.

Besides power performance, the cost of the system should be very low as well. This means that the circuitries should occupy a silicon area as small as possible and thus use a minimal number of discrete components. In the LO system, advantageously no extra inductors (this is also beneficial to alleviate the power amplifier (PA)-to-LO coupling problem) and no extra filtering modules are used. Moreover, the quadrature phase generation is dictated by the I/Q receiver scheme as a compromise of performance and cost. To achieve above requirements, the following conventional LO architectures can be found, as shown in Fig. la-d.

Fig. la shows the conventional LO system architecture with a quadrature voltage controlled oscillator (VCO) 10 and two buffers 1 1 , where frco=fLo- Fig. lb shows a known local oscillator system architecture using a VCO 10, buffer 1 1 , and an even-division-ratio divider 12,

Fig. lc shows a further known local oscillator system architecture using a VCO 10, buffer, and an odd-division-ratio divider 13 followed by quadrature generator 14,

Finally, Fig. Id shows an even further known local oscillator system

architecture using a VCO 10 and buffer 1 1 , and subsequently connected mixer 16 (with divider unit 15, filter unit (sideband selection and spur reduction) 17 and quadrature generator 14,

Among the above schemes, (a) is the most straightforward one, but it may have pulling problem because the LO frequency (so as the RF carrier frequency) equals the voltage-controlled oscillator (VCO) frequency.

With a divide-by-two divider, the method (b) is a well compromise between power and quadrature phase accuracy. However, it requires a high suppression level of the second harmonic of the transmitter output. To avoid pulling/coupling problems, higher division ratios N could be chosen instead (like divide by four or eight), but this leads to a higher VCO 10 frequency and thus much higher power consumption of the buffers 1 1 and the divider 12 itself.

Dividing by an odd number is better for pulling avoidance as shown in (c), but there is no easy quadrature output from it (particularly when a low supply voltage is used), so an extra phase generation circuit (quadrature generator 14) is normally required, which is either lossy or bulky or power hungry.

Methods like (d) are based on the idea of producing a fractional relation between the VCO 10 to LO frequencies to avoid pulling and coupling. Various implementations can be found in the prior art, but they are more complicated and related to other schemes.

Based on the above examples, the following considerations were accounted for in the present invention embodiments: (1) for a low power consumption the frequency of LO circuits (e. g. buffers, gain stages, dividers, etc.) should be kept as low as possible. In digital designs the power dissipation relates to a linear function of the clock frequency. In analog designs this applies also because at lower frequencies, the parasitic effects are less dominating, and thus less power is dissipated to achieve the same functions. Based on this point, the schemes with high-division-ratio dividers and high-frequency VCO 10 and buffers 11 are not suitable.

(2) the best amplifier is an oscillator (in general, a positive feedback system) if the linearity is not the concern, which is true in a local oscillator system.

(3) to avoid pulling, it is preferred to where M and N are positive integers, N≠l and M≠N.

The consideration (1) clearly indicates the power benefit of lowering the LO frequency. One popular method is the subsampling scheme, i.e. using a very low frequency LO to sample the incoming RF signal. This is e.g. disclosed in the article by De Vries et al. mentioned above. In this way, the LO power can be significantly reduced. However, in this known implementation a high-Q anti-aliasing filter is required in the receiver chain which increases the overall cost.

In view of consideration (2), an injection- locked oscillator could be used as the gain/buffer stage, which generates very high output level when locked with a small input. In a known system, an injection- locked ring oscillator (ILRO) based quadrature generation scheme is used, wherein an even-number-stage ring oscillator is used as the oscillator core, which inherently generates the desired quadrature outputs. Due to its low-Q nature a ring oscillator (especially the low-power and inductor- free ones) is noisy, but when it gets locked, the phase noise of the ILRO would become a replica of its input and thus can be clean enough. Unlike the divider, the input and output of the ILRO are identical and thus the requirement of high-frequency (high-power) VCO buffers is eliminated. The ILRO method is adopted in the system as disclosed in the article by Jianhua Lu et al., as mentioned above, to realize quadrature LO phases of a divide-by-three divider. However, this known system is still based on the idea of a high-frequency VCO with high-division-ratio, which is not good for the power consumption.

Consideration (3) suggests using a fractional relation between the VCO 10 and LO/RF frequencies to avoid pulling. In an exemplary implementation of such a fractional relation, an up-conversion mixer is used in the LO chain to convert a 1.6 GHz VCO frequency to a 2.4 GHz LO signal. However, a lot of spurs will show up with the desired LO which force an on-chip LC filter being used, which increases the overall cost and introduces a possible PA-to-LO coupling.

The present invention embodiments offer an optimum local oscillator generation solution with ultra-low power consumption and pulling-free performance. It should be noted that the disclosed invention can be implemented in various forms (e. g. by choosing different implementation details for any block or blocks) and the

embodiments described below are provided by way of example only. The local oscillator system can be applied in various applications as well. The application scenario mentioned in this document is also an example only, and not meant to be exhaustive.

The present invention embodiments relate in general to a combination 1 of a local oscillator system and a sub-harmonic mixer 7 for performing as a down-converter or a up-converter, comprising an oscillating signal generator 2, a quadrature phase generation unit 4 based on an injection locking method connected to an output of the oscillating signal generator 2, and a sub-harmonic mixer 7 (which comprises the functionality of frequency multiplication of the oscillating generator output) connected to an output of the quadrature phase generation unit 4. The oscillating signal generator 2 operates at a first frequency /vco which is a sub-harmonic of the operational frequency /LO- The quadrature phase generation unit 4 operates at half of the LO frequency. This is illustrated in the general block diagram as shown in Fig. 2, wherein the quadrature phase generation unit 4 and (part of) the sub-harmonic mixer 7 are forming a down-converter or a up-converter depending on using in the receiver or transmitter. In other words, all main components of the combination operate at sub- harmonic frequencies of the operational frequency _/Lo (i.e. the left part la as indicated in Fig. 2) and only in a final stage part (i.e. frequency multiplication in the sub- harmonic mixer 7) the operational frequency _/Lo is virtually present (i.e. the right part lb as indicated in Fig. 2). In more general terms, the oscillating signal generator 2 may operate at a frequency o/2N (wherein f ₀ is the same as the operational frequency /LO), as well as the quadrature phase generation unit 4. In the right part lb, an RF input signal is input to the sub-harmonic mixer 7, which implements the multiplication to /o/2N*N*2, resulting in an output IF signal at as in a regular IF generation using the operational frequency /LO-

Taking into account the considerations (l)-(3) described above, in a further embodiment, the first frequency ( vco) is equal wherein M and N are positive integers, N≠l, and M=l. This way, the above mentioned considerations - (1) lower LO frequency, (2) best amplifier is an oscillator and avoids pulling - are taken into account, and most LO circuits operate at a low frequency, which is a sub-harmonic of the desired RF frequency (operational frequency /LO).

As shown in the generalized diagram of Fig. 2 a sub-harmonic mixer 7 is added at the output of the quadrature phase generation unit 4, to get the desired frequency fo back (Note that the desired frequency is shown in the drawings as fo, and is equal to the operational frequency /LO as used in the claims and description). The required quadrature phase I, Q is generated by a low-cost, inductor- free injection locked oscillator 6 as implementation of the quadrature phase generation unit 4. Unlike the divider based methods, no frequency translation is needed in this step, so the high VCO frequency is not needed. Meanwhile, this block 4 is re-used as the VCO buffer to provide VCO-to-LO isolation and the required gain. The LO phase noise is now determined by the LC-based VCO embodiment of the oscillating signal generator 2 which is at much lower frequency, so the overall phase noise will not be degraded compared to the frequency division scheme based LO systems.

When it is assumed that most of the design of the present local oscillator system is a digital design (e. g. inverter based buffers or logic gates based function clocks), then the power consumption of each block (except the VCO 2) is linearly proportional to its operating frequency. The benchmark LO system (e.g. a divide by 2 embodiment of the prior art system shown in Fig. lc) consumes a power of oplus the VCO power while the system embodiment of Fig. 2 consumes P _O /N+P _M plus the VCO power, where P _M is the power consumed by the sub-harmonic mixer 7. If P _M is smaller than ((N- \)IN)-Po, the overall power will be lower.

Note that when the injection locking based quadrature generation unit 4 is implemented as a ring oscillator (inverter ring, e.g. as injection locked oscillator 6) for the sake of cost reduction, its power consumption corresponds to the one of a VCO buffer 11 that is needed anyway for the conventional LO systems (as illustrated in Figs, la-d). It should be pointed that though in Fig. 2 part of the frequency multiplication can happen before the subharmonic mixer 7 (when N is non-equal to 1). Moreover, the sub-harmonic mixer 7 can be passive, and thus no power is dissipated. With the sub- harmonic LO system of the embodiment shown in Fig. 2 the signal input level from the VCO 2 to the injection-locked oscillator 4 is relatively high. It is likely that the influence of the VCO injection signal will present in the injection locked oscillator output, which leads to an I/Q mismatch. To solve this issue, a (class- AB)

transconductance stage 5 can be used as the injection port (i.e. the dashed block in Fig. 2), which converts the injection voltage into current, so the bias condition of the secondary oscillator circuitry is not modulated by the injector. Meanwhile, by separating the injection terminal, there will be much less direct capacitive leakage to the output. Last but not least, the self-limiting behavior of the transconductance stage 5 is also helpful to alleviate the AM-to-PM (amplitude to phase) error. In general wording, a transconductance interface 5 is connected between the oscillating signal generator 2 and the quadrature phase generation unit 4 in a further embodiment. Note that the transconductance interface 5 may be implemented as one of an active transconductance stage 5 or a passive transformer stage 5. In such case, the quadrature phase accuracy is only determined by the injection locked oscillator 6 itself (i.e. mainly determined by the matching of its transistors) but not the VCO input. In order to make the invention clearly understood, some preferred embodiments are described in the following paragraphs.

Fig. 3 shows an embodiment of the subharmonic local oscillator system as part of a receiver system 20 using an injection locked ring oscillator (ILRO) as

implementation of the quadrature phase generation unit 4. The local oscillator system in this embodiment operates mainly at half of the local oscillator frequency ^LO- Such an ILRO is known in itself to the skilled person. In this embodiment, the oscillating signal generator 2 is one of a voltage controlled oscillator (VCO) or a digital controlled oscillator (DCO). Also, these functional blocks are known as such to the skilled person, and are easy to incorporate in the local oscillator system design.

The VCO 2 operates at the half of the desired RF frequency (foil in the figure).

After the VCO 2, a 4-stage ILRO 24 is adopted to generate 8 phases with π/4 separation. Since the ILRO 24 is fully implemented as digital circuitry, i.e. inverter based, it is able to generate rail-to-rail outputs with ultra-low power consumption. In this way, the requirement of the VCO swing can be relaxed, and thus the VCO 2 itself could be low power as well. Up to the frequency recovery block (mixers 22, 23) the LO circuitry operates at the sub-harmonic frequency foil. In this particular example, the frequency recovery circuit 7 is now only achieved by the front end mixers 22, 23, i.e. the sub-harmonic mixers. The sub-harmonic mixers 22, 23 will double the frequency to fx, and use it to down convert the input RF signal 21. So the frequency conversion behavior of the Rx mixer (assuming a zero-IF Rx) is #^ co*2± o.

One particular feature in this embodiment is to use an m: 1 transformer 5 to inject the VCO output to the ILRO 24. In such a way, the effective injection voltage swing is smaller while the current is higher (similar function as the above mentioned gm stage 5 described with reference to the Fig. 2 embodiment) without causing extra area (cost) or power requirements.

The power consumption comparison of the above exemplary embodiment of Fig. 3 compared with a conventional divide-by-two divider based LO system (Fig. lc) is listed in the following table.

The frequency multiplication can be partly merged with the injection locking quadrature phase unit 4 as well. For instance, the required LO frequency

translation/recovery can be implemented using an injection- locked frequency doubler (ILFD) or an injection- locked frequency tripler (ILFT), as illustrated in the

embodiments of Fig. 4a and b, respectively. Thus in a further embodiment, the quadrature phase generation unit 4 and at least part of the frequency multiplication functionalities are combined implemented in an injection locked frequency doubler

(ILFD) 25. Alternatively, the quadrature phase generation unit 4 and at least part of the frequency multiplication functionalities are combined implemented in an injection locked frequency tripler (ILFT) 28. In these case N>1.

Note that in some articles and books, the term ILFD is interpreted as the injection- locked frequency divider, but in this description and the claims it refers to injection- locked frequency doubler only.

In these exemplary embodiments, the natural (free running) frequency of the ring oscillator core of the ILFD 25/ILFT 28 is tuned to fo/N where frco=fo/2N. Before the core circuitry, there is an extra second/third harmonic generation module, or in general wording, a harmonic generator unit 27 connected to an output of the oscillating signal generator 2.

E.g. in the Fig. 4a example, in the ILFD 25, the common-mode node of a differential pair would contain a high second harmonic component, and thus can be used as the injection stage (to replace the gm stage 5 in Fig. 2, and form the harmonic generator unit). In this case, fvcc fo 4, and after the ILFD 25, the frequency is recovered to fo/2, which will be used to drive the sub-harmonic mixer 7.

In the ILFT example of Fig. 4b, a class-C stage 27 can be added and connected to an output of the oscillating signal generator 2 to manipulate the input pulse shape, so the power level of the third harmonic component is increased accordingly. Thus, the class-C stage acts as the (third) harmonic generator unit 27, and it is used to manipulate the injection signal sideband power. For example, if the injection frequency is to be tripled, the 3rd harmonic of the injection signal is required to be strong. As a result, a class-C stage is a good choice as the harmonic generation unit 27. In this case, fvcc fo 6, and after the ILFT 28, the frequency is recovered to fo/2, which will be used to drive the subharmonic mixer 7.

In general, by using a non-linear pulse shape/width control stage as the harmonic generator unit 27, any order sub-harmonic injection locking can be realized in the present invention local oscillator system embodiments. However, it is noted that with higher injection order, the locking range of the system will decrease (due to less injection power), and certain amount of power has to be dissipated to maintain the desired locking range. The present invention embodiments also relate to an integrated circuit comprising a local oscillator system according to any one of the embodiments described herein, e.g. in the form of a receiver circuit, transmitter circuit or transceiver circuit. This allows for example a low cost on-chip implementation of a radio application integrated circuit.

In the receiving mode of such an integrated circuit, a large in-band interference may be received by the antenna and then amplified by the LNA together with the desired RF signal. This large interference would leak through the substrate or the (passive) mixer itself to the local oscillator system part and pull the frequency away from the desired RF frequency / O and/or impair the local oscillator phase noise performance. This is schematically shown in the diagram of Fig. 5.

In general, it is not an issue in the present embodiments due to fact that the entire local oscillator system part is at the sub-harmonic frequency /vco that is sufficiently far from the interference frequency, and the phase generation and buffering is realized by a ring oscillator based injection locking system (i.e. ILRO 24 in the Fig. 5 embodiment) where no inductors (thus no magnetic coupling) are involved. It is also possible that when the locking range of the ILRO 24 is too large (due to its low Q nature and high injection power), the second harmonic frequency lies nearby or even within this locking range, but the ILRO's natural (free running) frequency will not be pulled because the interference injection is in-phase in both I and Q output nodes, so they will cancel with each other in the loop.

In the transmitting mode, the direct magnetic coupling between the power amplifier (PA) and VCO inductors are main reason of VCO pulling issue, which is also not an issue in the present invention embodiments of the local oscillator system simply because they are at different frequencies. In the conventional divide-by-two based LO system like in Fig. lc, the second harmonic of the PA output signal may still play a considerable role and potentially would pull the VCO frequency, especially when the PA output power is high and PA load mismatch is severe. This is again not an issue in the present invention embodiments.

As illustrated above referring to a number of exemplary embodiment, a low-cost local oscillator system is provided which is low power and pulling free. It is based on sub-harmonic frequency/phase generation, signal amplification and distribution. In one group of embodiments it uses a low-cost injection locked (ring) oscillator 24 combined with a transconductance (pre-injection) interface 5 that functions as both the quadrature phase generation unit 4 and as VCO buffer, which runs (also) at the sub-harmonic frequency. The frequency is recovered at the last block of the LO chain, this last block is the only module working at a high frequency.

The present invention embodiments have been described above with reference to a number of exemplary embodiments as shown in the drawings. Modifications and alternative implementations of some parts or elements are possible, and are included in the scope of protection as defined in the appended claims.