Computer-implemented method for calibrating a "phase-locked loop <PLL>" -based signal clean-up circuit and calibration system

The invention refers to a computer-implemented method for calibrating a "phase-locked loop <PLL>" based signal clean-up circuit according to the preamble claim 1 and a calibration system according to the preamble claim 13 .

According to https : / / powersimtech . com/ resources/ tutorials/ implement a tion- and-de s i gn-o f -pl 1- and- enhanced-pll -blocks/ "phase-locked loop ( PLL ) " -technology ( e . g . , PLL-circuits ) have been widely used in many engineering applications . The primary function of the PLL-principle behind the technology is to generate a clean, unitary signal which is synchronous with a noisy input signal where the amplitude and frequency can change with time . This is required in almost all technical systems that are interfaced with an AC power grid and are intended to interact with it in an active and controlled manner . This includes grid- connected inverters , recti fier loads , motor drives , and battery chargers .

The PLL-technology has also been extended to perform secondary tasks such as estimation of signal attributes including the magnitude , frequency, harmonics , sequence components , etc .

Another important task of the PLL-technology in power electronics and power system-based technology is to estimate the grid impedance to control the stability of the system .

From the cited reference it is known a conventional singlephase PLL ( 1-phase PLL ) has a very simple yet robust structure . The block diagram of the conventional PLL based on a proportional integral controller, called as Pl-controller ,

SUBSTITUTE SHEET (RULE 26) with the definitions of signals, is shown in Picture 1. Due to the presence of large double-frequency ripples, the single-phase PLL is not suitable for applications that require high level of accuracy.

The Picture 1 shows a conventional single-phase PLL with the following PLL-parameter: u(t) = input signal to the PLL coo = rated frequency of the input y(t) = unitary output signal synchronous with the input y' (t) = unitary output signal 90-degree delayed version of y(t) estimated angle w = estimated frequency in rad/sec. kp = proportional gain ki = integrating gain

It is further known from the cited reference a conventional triple-phase PLL (3-phase PLL) , which does not have the problem of the double-frequency ripple due to the fact that the ripples of the three phases cancel each other. However, when the 3-phase inputs are not balanced, the double-frequency ripple will be present.

The block diagram of the conventional 3-phase PLL, with the definitions of signals, is shown in Picture 2.

The Picture 2 shows a conventional triple-phase PLL with the following PLL-parameter: u(t) = input signal to the PLL coo = rated frequency of the input y(t) = unitary output signal synchronous with the input y' (t) = unitary output signal 90-degree delayed version of y(t) estimated angle w = estimated frequency in rad/sec.

SUBSTITUTE SHEET (RULE 26) ud = d-axis component of the input uq = q-axis component of the input uo = zero-axis component of the input kp = proportional gain ki = integrating gain

The " abc/dqo" -trans formation is defined as :

Moreover, from the WO 2007 / 147649 A2 it is known a current source inverter and a method for uninterrupted switching of the current source inverter, which comprises means for operating the inverter in fundamental frequency unregulated operation, means for operating the inverter in clocked voltage regulated operation, means for recording parameters from which conclusions can be drawn at an instantaneous operating point and/or at an instantaneous network condition, means for determining an appropriate operating condition from the recorded parameters and means for uninterrupted switching of the operation of the inverter to the operating condition as determined from the recorded parameters .

Furthermore , from the DE 10 2012 209227 Al it is known a method, an apparatus , and a system of measuring frequency, wherein

- a first number of full cycles of a signal at a rate based on a nominal frequency of the signal are sampled,

- the samples to digital samples are converted,

- the digital samples to identi fy a first pair of digital samples with each one disposed on either side of a first ze-

SUBSTITUTE SHEET (RULE 26) ro-crossing and a second pair of digital samples with each one disposed on either side of a last full cycle zerocrossing are processed,

- the first pair of digital samples and the second pair of digital samples to determine a position of the first and last zero-crossings relative to each other in time ; and calculating a fundamental frequency of the signal based on the first number of full cycles sampled and the relative position of the first and last zero-crossings are interpolated .

It is an obj ective of the invention to propose a method for calibrating a "phase-locked loop <PLL>" based signal clean-up circuit and a calibration system, by which the calibration is done automatically

( i ) to avoid the necessity of technical experts because of no well-established rules exist between sampling/ lock-on frequency and PLL-parameters for calibrating the PLL-parameter

( ii ) to bypass trial-and-error approaches by connecting the PLL-circuit to a technical system before moving on with a control of the technical system, e . g . , an AC power grid with electric power converter before moving on with the control of the converter

( iii ) although conventional PLL-circuits may show slow convergence and/or instability for unfavorable noise distributions , distorted input signals or fault scenarios

( iv) even though conventional PLL-circuits cannot automatically optimi ze themsel f for di f ferent sample frequencies or lock-in frequencies during runtime .

This obj ective is solved regarding to a method defined in the preamble of claim 1 by the features in the characteri zing part of claim 1 .

Furthermore , the obj ective is solved regarding to a calibration system defined in the preamble of claim 13 by the features in the characteri zing part of claim 13 .

SUBSTITUTE SHEET (RULE 26) The main idea of the invention according to the claim 1 - in order to calibrate a "phase-locked loop <PLL>"-based signal clean-up circuit on the basis of input values, in particular related to at least one phase, e.g., a "1-phase" related input values or "3-phase"related input values, being received for a calibration process and belonging to a noisy input signal with an amplitude and a frequency dynamically changed and being synchronous with a clean, unitary signal of the signal clean-up circuit - consists in

- training a machine-learning module (i) by samples of generated training data regarding (il) a sampling-frequency used for the training "fs_train", (i2) a random lock-in-frequency used for the training and around a defined target, in particular an average target, "fO_train" and (i3) random noise and distortions of the received input values, and (ii) according to generated machine learning module weights,

- preprocessing the received input values regarding samplingfrequencies "fs", being each equal or unequal to the training-used sampling-frequency "fs_train", and lock-in- frequencies "fO", being each equal or unequal to the training-used lock-in frequency "fO_train", by combining multiple adjustable delays and multiple threshold counters with variable increment to enable a reconfiguration of each the sampling-frequency "fs" and each the lock-in-frequency "fO" without retraining the machine learning module weights,

- inputting the preprocessed input values into the trained machine-learning module,

- providing by the trained machine-learning module estimated, weighted output values related accordingly to the received input values.

The presented approach enables that (1) a PLL-parameter calibration can be done by non-experts as the sampling frequency, the lock-on frequency and PLL-parameters can be set directly. Thus, a simplified rapid prototyping and simulations can be achieved for different control architectures, e.g., 50Hz/60Hz AC power grids, (2) the "machine-learning module"-based training for the PLL-calibration ensures optimal tuning to a

SUBSTITUTE SHEET (RULE 26) wide range of noise distributions , distortions , and fault scenarios as well as fast lock-in time , ( 3 ) the "machinelearning module" -based training for the PLL-calibration can automatically sel f-optimi ze its performance during runtime for wide range of sample frequencies and lock-in frequencies by automatic dynamic reconfiguration, and ( 4 ) it is solved the issue that "machine-learning module" -based solutions generally required continuous output which is not the case for the "phase-locked loop <PLL>" -based signal clean-up circuit .

The described approach is designed according to claim 13 for a calibration system, which can be preferably used as a com- puter-implemented-tool embodied for instance as a Computer- Program-Product being designed as an "APP" .

The calibration system, which is based on ( i ) a non- transitory, processor-readable storage medium having processor-readable program-instructions of a program module stored in the non-transitory processor-readable storage medium and ( ii ) a processor connected with the storage medium executing the processor-readable program-instructions of the program module , is designed such that ( 1 ) the program module includes either a training data generator, a machine-learning module and a preprocessing entity or a training data generator, a machine-learning module , a preprocessing entity and a postprocessing entity, and ( 2 ) the processor executes the processor-readable program-instructions of the program module and thereby accesses to the included components to execute the described approach .

Further advantageous developments of the invention are specified and given in the dependent claims .

So according to the claim 2 it would be an advantage of the invention that the multiple counters are initiali zed for a defined threshold on y-coordinate axis , a defined input phase on x-coordinate axis and a type of y-coordinate level cross-

SUBSTITUTE SHEET (RULE 26) ing, e.g., positive and/or negative, wherein for each counter a logic is applied such that: a) in each cycle the counter is incremented by base increment values "incv_base" b) the counter is reset each time the received input values crosses its defined threshold and count direction.

An example is provided in Picture 3 for positive direction crossing and thresholds at 0 (red lines in the Picture 3) , 0.5 (orange lines in the Picture 3 ) , 0.9 (light orange lines in the Picture 3 )

The Picture 3 shows an illustration of the multiple counters with vector of thresholds =[-0.5, 0., 0.5, 0.97 ...] and the base increment values "incv_base".

Furthermore, it would be advantageous according to the claim 3 that an delay length "DL" using integer multiples of an base delay "D_base=x samples" is instantiated depending on the sampling-frequencies "fs" being required and a counter increment of the counters, which based on the training-used sampling-frequency "fs_train" and the training-used lock-in- frequency "f0_train" is initialized to a primary-base increment value "incv_base_p~f 0_train/f s_train" of the base increment values "incv_base".

In addition, according to the claim 4, the invention is developed advantageously by reconfiguring the lock-in-frequency from the lock-in-frequency "fO" to a new lock-in-frequency "f0_new" according to which

- a base delay adjustment changed from the base delay primary base delay 0_new) samples" and

- a counter increment change from the primary-base increment value "incv_base_p~f 0_train/f s_train" to a secondary-base increment value "incv_base_s~f 0_new/f s_train" of the base increment values "incv base" are carried out.

SUBSTITUTE SHEET (RULE 26) As an alternative option in advantageously developing the invention according to the claim 5 the sampling-frequency "fs" reconfiguration from the training-used sampling-frequency "fs_train", e.g., " f s_train=8kHz " , to a new sampling frequency "fs_new", e.g., " f s_new=12kHz " , comprises

- a further base delay adjustment changed from the base delay "D_base=x samples" to a secondary base delay

"D_base_s~x* ( f s_new/ f s_train) samples", e.g., the base delay "D_base=6* ( 12kHz/8kHz ) =9 samples", and if needed or necessary, a result of the calculated second fraction is rounded to an integer next to the result,

- a counter increment change from the primary-base increment value "incv_base_p~f 0_train/f s_train" to a tertiary-base increment value "incv_base_t~f 0_new/f s_new" of the base increment values "incv_base".

As a further alternative option in advantageously developing the invention according to the claim 6 the sampling-frequency "fs" reconfiguration from the training-used samplingfrequency "fs_train", to a new sampling frequency "fs_new" comprises

- a further base delay adjustment changed from the primary base delay "D_base_p~x* ( f 0_train/f 0_new) samples" to a tertiary base delay

"D_base_t~x* ( f 0_train/f 0_new) * ( f s_new/f s_train) samples", and if needed or necessary a result of the calculated second fraction is rounded to an integer next to the result,

- a counter increment change from the secondary-base increment value "incv_base_s~f 0_new/f s_train" to a tertiary-base increment value "incv_base_t~f 0_new/f s_new" of the base increment values "incv_base" .

Moreover, according to the claims 7 to 9 it is particularly advantageous that (i) the noisy input signal inputted into the signal clean-up circuit and (ii) the signal clean-up circuit belong to a technical system that is interfaced with an

SUBSTITUTE SHEET (RULE 26) AC power grid and is intended to interact with it in an active and controlled manner.

Following this beneficial approach, where the technical system including the signal clean-up circuit and interfacing with the AC power grid to interact with it in the active and controlled manner, it is favorably chosen according to the claim 8

(1) to use the training-used sampling-frequency "fs_train" as "8kHz",

(2) to use the sample number "x" of the base delays and the new base delays as "x=6" to support by the training-used lock-in frequency "fO_train" a 50Hz-f requency of the AC power grid and to use by the new lock-in frequency "fO_new" a 60Hz- frequency of the AC power grid and

(3) to use the delay length "DL" with the sample number "x=6" as " [1,2,4,8,16]* [D_base=6] = [ 6, 12, 24, 48, 96]

An exemplary simulation-based connection diagram with respect to a possible preprocessing entity and a machine-learning module concerning the scenario presented above by (1) to (3) is shown in Picture 4. According to this depicted scenario and in addition, a sample with a single delay is fed into the module to realize the counter logic according to the claim 2 (cf. explanations above i.c.w. the Picture 3) .

The Picture 4 shows an exemplary simulation-based connection diagram providing inputs and outputs for initialization at "fO_train"= 50Hz, "fs_train"= 8kHz.

Further following this beneficial approach regarding the lock-in-frequency reconfiguration from the lock-in frequency "f0=50Hz" to the new lock-in-frequency "f 0_new=60Hz" according to the claim 9 it is proposed

(a) the base delay adjustment from the base delay "D_base=6 samples" to the first new base delay "D_base=6* ( 50Hz/ 60Hz ) =5 samples", which adapts a new delay length "DL" with the new

SUBSTITUTE SHEET (RULE 26) sample number "x=5" as " [1,2,4,8,16,

...] * [D_base=5] = [5, 10, 20, 0, 80, ...] " and

(b) the counter increment change from the increment value "inc_f=f 0_train/f s_train=50/8000" to a new increment value "inc_f = f 0_new/f s_train=60/8000" .

An exemplary simulation-based connection diagram with respect to a possible preprocessing entity and a machine-learning module concerning the scenario presented above by (a) to (b) is shown in Picture 5. Also, according to this depicted scenario and in addition, a sample with a single delay is fed into the module to realize the counter logic according to the claim 2 (cf. explanations above i.c.w. the Picture 2) .

The Picture 5 shows an exemplary simulation-based connection diagram providing inputs and outputs for initialization at "f0_train"= 60Hz, "fs_train"= 8kHz.

Beyond the aforementioned advantageous developments of the invention, it is beneficial

- according to the claim 10 that the signal clean-up circuit is a triple phase PLL-circuit where the estimated, weighted output values are postprocessed combined via median filtering for improved robustness, and/or

- according to the claim 12 that the machine-learning module is an artificial neural network, a Bayesian neural network, a recurrent neural network, a convolutional neural network, multilayer perceptron, autoencoder, support-vector-machine, a data-driven trainable regression model, a k-nearest neighbor regressor, a physical model, a deep neural network regressor and/or a decision tree regressor.

Last but not least it is advantageous according to the claim 11 that the reconfiguration is done dynamically by inversely setting the base delay adjustment and the counter increment change proportional to the estimated, weighted output values.

SUBSTITUTE SHEET (RULE 26) Besides the above , advantageous further developments of the invention arise out of the following description of a preferred embodiment of the invention according to a single FIGURE .

The FIGURE shows the principal design or structure of a calibration system CBSY for calibrating a "phase-locked loop <PLL>" -based signal clean-up circuit SCUC, which belong to a technical system TSY that is interfaced preferably with an AC power grid ACPG and is intended to interact with it in an active and controlled manner . This includes for example grid- connected inverters , recti fier loads , motor drives , and battery chargers . In this context the AC power grid ACPG provides a noisy input signal IPS _n inputted into the signal clean-up circuit SCUC . The noisy input signal IPS _n includes an amplitude and a frequency dynamically changed and being synchronous with a clean, unitary signal of the signal cleanup circuit SCUC .

For the cited purpose the calibration system CBSY carries out a calibration process to calibrate the "phase-locked loop <PLL>" -based signal clean-up circuit SCUC, wherein the calibration process includes a training process TDG, MLM, trn, a preprocessing process PRPE , prpc, and an estimating process MLM, ipt , pvd .

The calibration system CBSY is preferably designed as a com- puter-implemented-tool CIT , which for example is embodied as a Computer-Program-Product being designed as an "APP" APP, and includes a non-transitory, processor-readable storage medium STM, e . g . , a Random Acces Memory <RAM>, having processor-readable program-instructions of a program module PGM stored in the non-transitory processor-readable storage medium STM and a processor PRC connected with the storage medium STM executing the processor-readable programinstructions of the program module PGM .

SUBSTITUTE SHEET (RULE 26) In the purposeful context the program module PGM includes essentially a training data generator TDG, a machine-learning module MLM and a preprocessing entity PRPE . In addition, it is optionally possible that the program module PGM includes a postprocessing entity POPE , which accordingly is depicted in dashed lines .

In the same context for carrying out a calibration process to calibrate the "phase-locked loop <PLL>" -based signal clean-up circuit SCUC the processor PRC executes the processor- readable program-instructions of the program module PGM and thereby accessing to the training data generator TDG, the machine-learning module MLM and the preprocessing entity PRPE and i f necessary, the postprocessing entity POPE .

The calibration process includes a training process TDG, MLM, trn, a preprocessing process PRPE , prpc, and an estimating process MLM, ipt , pvd supplemented optionally by a postprocessing process POPE , pope .

Generally, the starting point for a calibration process is the presence of data . So , in the present case the "phase- locked loop <PLL>" -based signal clean-up circuit SCUC receive rev input values IPV of the noisy input signal IPS _n . These input values are preferably in the case of the AC power grid ACPG input values related to at least one phase IPV _ph , e . g . , a " 1-phase" related input value IPVi- _P h ( cf. Pi cture 1 i . e . w. the corresponding explana ti ons ') or " 3-phase" related input values IPV3- _P h ( cf. Pi cture 2 i . e . w. the corresponding expla na ti ons ') .

To carry out the calibration process it is first required that according to the training process TDG, MLM, trn, when the processor PRC accesses to the training data generator TDG, the machine-learning module MLM and the preprocessing entity PRPE of the program module PGM, the machine-learning module MLM is trained trn by samples of training data generated by the training data generator TDG .

SUBSTITUTE SHEET (RULE 26) Training is generally understood to mean an optimi zation of a mapping from input data to output data of the machinelearning module MLM . This mapping is optimi zed according to predetermined criteria during a training phase . A prediction error in the case of prediction models , a classi fication error in the case of classi fication models , or a performance of a technical system controlled by the output data in the case of models of reinforcement learning can be used as criteria . The training can be used in particular to set or optimi ze network structures of neurons in a neural network, weights of connections between the neurons and/or other parameters of the mapping in such a way that the speci fied criteria are met as well as possible . The training can thus be regarded as an optimi zation problem . A large number of ef ficient optimi zation methods are available for such optimi zation problems of machine learning . In particular, gradient descent methods , back-propagation methods , particle swarm optimi zation and/or genetic optimi zation methods can be used .

Against this technical background the machine-learning module MLM is preferably an arti ficial neural network, a Bayesian neural network, a recurrent neural network, a convolutional neural network, multilayer perceptron, autoencoder, supportvector-machine , a data-driven trainable regression model , a k-nearest neighbor regressor, a physical model , a deep neural network regressor and/or a decision tree regressor .

In the present case the machine-learning module MLM is trained trn by the samples of the training data generated in the training data generator TDG, when the processor PRC

- regarding a sampling- frequency used for the training " fs_train" , a random lock-in- frequency used for the training and around a defined target " f O_train" , which could be for example an average target , and random noise and distortions of the received input values IPV, IPV _ph , IPVi- _ph , IPV _3-ph , and

- according to generated machine learning module weights MLMW .

SUBSTITUTE SHEET (RULE 26) The training process TDG, MLM, trn can be advantageously carried out of fline from the actual calibration process .

In the reprocessing process PRPE , prpc, when the processor PRC accesses to the preprocessing entity PRPE of the program module PGM, the received input values IPV, IPV _P h, IPVi- _P h, IPV3- _P h regarding sampling- frequencies " fs" and lock-in- frequencies " f O" are preprocessed prpc by the preprocessing entity PRPE by combining multiple adj ustable delays and multiple threshold counters with variable increment to enable a reconfiguration of each the sampling- frequency " fs" and each the lock-in- frequency " f O" without retraining the machine learning module weights MLMW .

The sampling- frequencies " fs are each equal or unequal to the training-used sampling- frequency " fs_train" and the lock-in- frequencies " f O" are each equal or unequal to the training- used lock-in frequency " f O_train" .

In the estimating process MLM, ipt , pvd, when the processor PRC accesses to the preprocessing entity PRPE and the machine-learning module MLM of the program module PGM, the pre- processed input values are inputted ipt into the trained machine-learning module MLM and the trained machine-learning module MLM provides pvd estimated, weighted output values OPV related accordingly to the received input values IPV, IPV _P h, IPVi_ _ph , IPV _3-ph .

Furthermore , the reprocessing process PRPE , prpc, when the processor PRC accesses to the preprocessing entity PRPE of the program module PGM, is further designed in such a way that

1 ) the multiple counters are initiali zed for a defined threshold on y-coordinate axis , a defined input phase on x- coordinate axis and a type of y-coordinate level crossing, e . g . , positive and/or negative , wherein for each counter a logic is applied such that

SUBSTITUTE SHEET (RULE 26) - in each cycle the counter is incremented by base increment values "incv_base",

- the counter is reset each time the received input values IPV, IPVph, IPVi-ph, IPV ₃ -p _h crosses its defined threshold and count direction.

2) a delay length "DL" using integer multiples of an base delay "D_base=x samples" is instantiated depending on the sampling-frequencies "fs" being required and a counter increment of the counters, which based on the training-used samplingfrequency "fs_train" and the training-used lock-in-frequency "fO_train" is initialized to a primary-base increment value "incv_base_p~f 0_train/f s_train" of the base increment values "incv_base" .

3) the lock-in-frequency reconfiguration from the lock-in- frequency "fO" to a new lock-in-frequency "fO_new" comprises

- a base delay adjustment changed from the base delay primary base delay 0_new) samples", and

- a counter increment change from the primary-base increment value "incv_base_p~f 0_train/f s_train" to a secondary-base increment value "incv_base_s~f 0_new/f s_train" of the base increment values "incv_base".

4) the sampling-frequency "fs" reconfiguration from the training-used sampling-frequency "fs_train", e.g.,

"f s_train=8kHz" , to a new sampling frequency "fs_new", e.g., "f s_new=12kHz" , comprises

- a further base delay adjustment changed from the base delay "D_base=x samples" to a secondary base delay "D_base_s~x* ( f s_new/ f s_train) samples", e.g., the base delay "D_base=6* ( 12kHz/8kHz ) =9 samples", and if needed or necessary a result of the calculated second fraction is rounded to an integer next to the result,

- a counter increment change from the primary-base increment value "incv_base_p~f 0_train/f s_train" to a tertiary-base in-

SUBSTITUTE SHEET (RULE 26) crement value "incv_base_t~f O_new/f s_new" of the base increment values "incv_base".

5) the sampling-frequency "fs" reconfiguration from the training-used sampling-frequency "fs_train", to a new sampling frequency "fs_new" comprises

- a further base delay adjustment changed from the primary base delay "D_base_p~x* ( f 0_train/f 0_new) samples" to a tertiary base delay

"D_base_t~x* ( f 0_train/f 0_new) * ( f s_new/f s_train) samples", and if needed or necessary a result of the calculated second fraction is rounded to an integer next to the result,

- a counter increment change from the secondary-base increment value "incv_base_s~f 0_new/f s_train" to a tertiary-base increment value "incv_base_t~f 0_new/f s_new" of the base increment values "incv_base" .

6) the reconfiguration is done dynamically by inversely setting the base delay adjustment and the counter increment change proportional to the estimated, weighted output values OPV, OPV' .

Beyond that what is described above, when - now according to a particular embodiment of the invention - the signal cleanup circuit SCUC belong to the technical system TSY that is interfaced with the AC power grid ACPG and for the calibration process "1-phase" related input values IPVi- _P h or "3- phase"related input values IPVs-ph, of the noisy input signal IPS _n are received rev, the reprocessing process PRPE, prpe, when the processor PRC accesses to the preprocessing entity PRPE of the program module PGM, is further designed in such a way that 1) it is favorably chosen

- the training-used sampling-frequency "fs_train" as "8kHz",

- the sample number "x" of the base delays and the new base delays as "x=6" to support by the training-used lock-in frequency "fO_train" a 50Hz-f requency of the AC power grid and

SUBSTITUTE SHEET (RULE 26) by the new lock-in frequency "fO_new" a 60Hz-f requency of the AC power grid (ACPG) and

- the delay length "DL" with the sample number "x=6" as " [1,2,4,8,16]* [D_base=6] = [6, 12,24,48,96]".

2) regarding the lock-in-frequency reconfiguration from the lock-in frequency "f0=50Hz" to the new lock-in-frequency

"f 0_new=60Hz" it is comprised

- the base delay adjustment changed from the base delay "D_base=6 samples" to the first new base delay "D_base=6* ( 50Hz/ 60Hz ) =5 samples", which adapts a new delay length "DL" with the new sample number "x=5" as " [1,2,4,8,16, ...] * [D_base=5] = [5, 10, 20, 40, 80, ...] " and

- the counter increment change from the increment value "inc_f=f 0_train/f s_train=50/8000" to a new increment value "inc_f = f 0_new/f s_train=60/8000" .

3) when the signal clean-up circuit SCUC is a triple phase PLL-circuit with the received "3-phase"related input values IPVs-ph and the estimated, weighted output values OPV are provided pvd by the trained machine-learning module MLM, the estimated, weighted output values OPV are postprocessed pope in the postprocessing entity POPE by corresponding accesses of the processor PRC according to the postprocessing process POPE, pope supplementing the calibration process optionally. This postprocessing process POPE, pope is characterized by combining the estimated, weighted output values OPV via median filtering for improved robustness and generating modified output values OPV' .

SUBSTITUTE SHEET (RULE 26) ANNEX

- PICTURES related to the speci fication -

Picture 1 : a conventional single-phase PLL

Picture 2 : a conventional triple-phase PLL

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Picture 3: Illustration of the multiple counters with vector of thresholds =[-0.5, 0., 0.5, 0.97 ...] and the base increment values "incv base"

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Picture 4 : Exemplary simulation-based connection diagram providing inputs and outputs for initialization at "fO train"= 50Hz, "fs train"= 8kHz

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Picture 5: Exemplary simulation-based connection diagram providing inputs and outputs for initialization at "fO train"= 60Hz, "fs train"= 8kHz

SUBSTITUTE SHEET (RULE 26)