Title:
COMPUTER SYSTEM
Document Type and Number:
WIPO Patent Application WO/2016/117102
Kind Code:
A1
Abstract:
A problem to be solved by the present invention is, in a computer system, to reduce processing delay from wait times which occur in timer access. According to the present invention, using either a CPU core (hereinafter "processing core") other than a CPU core which executes an application, or a DMA device, a latest timer value is always transferred from a timer device to a primary storage device. The processing core reads the transferred value upon the primary storage device instead of accessing a register of the timer device, thereby avoiding a wait which occurs when directly reading the timer value of the timer device. The transfer of the value is carried out asynchronously from the processing of the processing core, thus obviating the need for the processing core to wait for the completion of the transfer. Accordingly, it is also unnecessary for the processing core to process an interrupt or a notification from another CPU core or the DMA device.
Inventors:
SHIMOSAWA TAKU (JP)
KAWAI HIDEHIRO (JP)
MINE HIROSHI (JP)
OOSHIMA SATOSHI (JP)
KAWAI HIDEHIRO (JP)
MINE HIROSHI (JP)
OOSHIMA SATOSHI (JP)
Application Number:
PCT/JP2015/051753
Publication Date:
July 28, 2016
Filing Date:
January 23, 2015
Export Citation:
Assignee:
HITACHI LTD (JP)
International Classes:
G06F1/14; G06F13/00
Foreign References:
| JPS63292246A | 1988-11-29 | |||
| JPH1097445A | 1998-04-14 | |||
| JP2007328441A | 2007-12-20 | |||
| JPH06231087A | 1994-08-19 |
Attorney, Agent or Firm:
INOUE Manabu et al. (JP)
Manabu Inoue (JP)
Manabu Inoue (JP)
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