SIDEWALLS FOR FILAMENT LOCALIZATION

TECHNICAL FIELD

ibodiments of the invention are in the field of integrated circuit fabrication and, particular, approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewails for filament localization, and the resulting structures and devices. BACKGROUND

For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of

semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.

Embedded SRAM and DRAM have problems with non-volatility and soft error rates, while embedded FLASH memories require additional masking layers or processing steps during manufacture, require high-voltage for programming, and have issues with endurance and reliability. Nonvolatile memory based on resistance change is known as RRAM or ReRAM. Although commonly anticipated as a replacement technology for flash memory, the cost benefit and performance benefit of RRAM have not been obvious enough to most companies to proceed with the replacement. Also, for low voltage non-volatile embedded applications, operating voltages less than IV and compatible with CMOS logic processes may be desirable but challenging to achieve.

Thus, significant improvements are still needed in the area of nonvolatile memory device manufacture and operation. In particular, significant improvements are still needed in the area of non-volatile memory arrays and their integration with logic processors.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1A illustrates a cross-sectional view of a conductive bridge random access memory (CBRAM) element without sidewall engineering.

Figure IB illustrates a cross-sectional view of a CBRAM element having engineered sidewails and a localized filament, in accordance with an embodiment of the present invention. Figure 2 illustrates cross-sectional views of various operations in a method of fabricating a CBRAM element, in accordance with an embodiment of the present invention.

Figure 3 illustrates cross-sectional views of various operations in a method of forming a centralized filament in a CBRAM element, in accordance with an embodiment of the present invention.

Figures 4A-4C illustrate cross-sectional views of CBRAM elements having engineered sidewalls with varied dopant profiles, in accordance with an embodiment of the present invention.

Figure 5A illustrates a cross-sectional view of two CBRAM devices, in accordance with an embodiment of the present inventi on.

Figure 5B illustrates a plan view of a pair of CBRAM elements integrated with a common line electrode, in accordance with an embodiment of the present invention.

Figure 5C illustrates a plan view of a pair of CBRAM elements integrated with discrete via electrodes, in accordance with an embodiment of the present invention.

Figure 6 illustrates a cross-sectional view of a conductive bridge random access memory

(CBRAM) device fabricated using a damascene process, in accordance with an embodiment of the present invention.

Figure 7 illustrates a cross-sectional view of a conductive bridge random access memory (CBRAM) element coupled to a drain side of a transistor selector, in accordance with an embodiment of the present invention.

Figure 8A illustrates schematic views of several options for positioning a conductive bridge random access memory (CBRAM) element in an integrated circuit, in accordance with an embodiment of the present invention.

Figure 8B illustrates a cross-sectional view of a logic region together with a conductive bridge random access memory (CBRAM) memory array integrated on a common substrate, in accordance with an embodiment of the present invention.

Figures 9A and 9B illustrate a schematic and corresponding I-V plot, respectively, demonstrating concepts involved with filament formation in a conductive bridge random access memory (CBRAM) element, in accordance with an embodiment of the present invention.

Figure 10 illustrates an operational schematic representing a changing of states for a

CBRAM memory element, in accordance with an embodiment of the present invention.

Figure 1.1 illustrates a schematic representation of resistance change in a CBRAM:

induced by changing the concentration of cation vacancies in the electrolyte layer, in accordance with an embodiment of the present invention. Figure 12 illustrates a schematic of a memory bit cell which includes a CBRAM memory element, in accordance with an embodiment of the present invention.

Figure 13 illustrates a block diagram of an electronic system, in accordance with an embodiment of the present invention.

Figure 14 illustrates a computing device in accordance with one embodiment of the invention.

Figure 15 illustrates an interposer that includes one or more embodiments of the invention. DESCRIPTION OF THE EMBODIMENTS

Approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalls for filament localization, and the resulting structures and devices, are described. In the following description, numerous specific details are set forth, such as specific CBRAM material regimes and structure architectures, in order to provide a thorough

understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known features, such as operations associated with embedded memory, are not described in detail in order to not unnecessarily obscure embodiments of the present invention. Furthermore, it is to be appreciated that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.

Certain terminology may also be used in the following description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as "upper", "lower", "above", "below," "bottom," and "top" refer to directions in the drawings to which reference is made. Terms such as "front", "back", "rear", and "side" describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.

One or more embodiments are directed to conductive bridge random access memory (CBRAM) material stacks having doped sidewalls in an electrolyte switching layer. Particular embodiments are directed to the engineering of sidewalls of a switching layer in a CBRAM element for filament centralization. One or more embodiments of the present invention are directed to methods for integrating CBRAM memory arrays into a logic processor. Particular embodiments may be suitable for fabricating embedded non-volatile memory (e-NVM).

Approaches described herein may provide a fabrication pathway for high performance CBRAM: cells and increase the potential of using scaled CBRAM ceils for future e-NVM needs, such as for integration in system on chip (SoC) products.

In accordance with embodiments of the present invention, a CBRAM material stack is designed to improve the switching properties and reliability of a memory device based on the CBRAM materia] stack. It is to be appreciated that CBRAM may be viewed as a specific type of resistive random access memory (RRAM). In a CBRAM device, a filament is formed based on metallic migration into an electrolyte material which is the switching layer of the CBRAM device. By contrast, in conventional RRAM, a filament is created based on oxygen vacancies. In an embodiment, sidewalls of the electrolyte layer are doped with materials that prevent the diffusion of metal ions. As such, the resulting CBRAM element may be structured to ensure that a metal ion filament forms at the center of the CBRAM stack, e.g., that the filament is localized.

To provide illustrative context, Figure 1 A illustrates a cross-sectional view of a conductive bridge random access memory (CBRAM) element without sidewall engineering.

Referring to Figure 1 A, a CBRAM element material stack 100 includes a bottom electrode disposed above a substrate 101. A resistance switching layer 104 is disposed on the bottom electrode 102. A metal ion source layer 106 is disposed on the resistance switching layer 104. A top electrode 108 is disposed on the metal ion source layer 106.

Referring again to Figure 1A, the resistance switching layer 104 is an electrolyte layer.

Filaments 1 10A, 1 10B and 1 IOC are formed in the electrolyte layer with metal ions from the metal ion source layer 106. However, the presence of more than one filament and the lack of centralization of the filaments may lead to unwanted variability of an array of the CBRAM: elements 100.

By controlling the number and location of filaments formed in a CBRAM element, variability among an array of CBRAM: elements may be reduced. As an exemplar

implementation, Figure IB illustrates a cross-sectional view of a CBRAM element having engineered sidewalls and a localized filament, in accordance with an embodiment of the present invention.

Referring to Figure IB, a conductive bridge random access memory (CBRAM) device 120 includes a first electrode layer 122 disposed above a substrate 101, which may include a conductive interconnect underlying the CBRAM device 120. A resistance switching layer 124 is disposed on the first electrode layer 122. The resistance switching layer 124 includes an electrolyte material 126 having doped regions 129 at outermost ends of the electrolyte material 126 but not in a central portion of the electrolyte material 126. A metal ion source layer 130 is disposed on the resistance switching layer 124. A second electrode layer 132 is disposed on the metal ion source layer 30. In an embodiment, a filament 128 is included in the resistance switching layer 124 to provide filament-based CBRAM, as is described in greater detail below in association with Figures 9A and 9B. In one embodiment, the CBRAM device 120 includes only a single filament 128. The single filament 128 is disposed in the central portion of the electrolyte material 126, i.e., between but not within the doped regions 129. In other embodiments, however, a filament is not included and surface or interface-based CBRAM is fabricated. As such, embodiments described herein are applicable to both filamentary and interfaciai CBRAM implementations.

In accordance with an embodiment of the present invention, by controlling the formation of the metal filament, control of variability from cell to cell is achieved and, ultimately, reduced. Additionally, by ensuring that the filament forms at the center of the CBRAM stack, switching properties of the CBRAM device may not be impacted by process induced damage at the edges of the device. Certain dopants may reduce the diffusivity of metal ions in oxides, such as B, C, N, or F dopants. Such species may be included into an electrolyte by plasma processing.

Additionally, increasing the oxygen (O) content of a sub-oxide electrolyte by oxidizing from the sidewalis can also reduce the diffusivity of the metal ions around the sidewails.

Referring again to Figure I B, and as used throughout the present disclosure, in an embodiment, the electrolyte material 126 is a chalcogenide material or a metal oxide material. In one such embodiment, the electrolyte material 126 is a chalcogenide material such as, but not limited to, GeSb ₂ Te ₅ . In one such embodiment, the electrolyte material 126 is a metal oxide material such as, but not limited to, hafnium oxide.

In an embodiment, the doped regions 129 include dopant species such as, but not limited to, B, C, N, O or F. In one embodiment, the doped regions 129 at the outermost ends of the electrolyte material 126 have a depth into the outermost ends of the electrolyte material 126 approximately equal to a thickness of the resistance switching layer 124. In a specific such embodiment, the thickness of the resistance switching layer 124 is approximately in the range of 1-2 nanometers. In an embodiment, the central region of the resistance switching layer 124 that is an undoped or non-doped region of the electrolyte material 126 has a width approximately in the range of 2-4 nanometers.

Referring again to Figure IB, and as used throughout the present disclosure, in an embodiment, the metal ion source layer 130 includes a metal species such as, but not limited to, copper, silver, or lithium. In one embodiment, the metal ion source layer 130 is composed of copper telluride. In one embodiment, the metal ion source layer 130 is composed of silver telluride. In one embodiment, the metal ion source layer 130 is a lithium-containing layer such as a lithium-containing layer described below in association with Figures 10 and 11. Referring again to Figure IB, and as used throughout the present disclosure, the first electrode layer 122 and the second electrode layer 132 are conductive metal or metal alloy layers. In one embodiment, a metal nitride, such as a titanium nitride or a tantalum nitride layer, is used as the material for the first electrode layer 122 and/or the second electrode layer 132. In another embodiment, the first electrode layer 122 and/or the second electrode layer 132 is composed of a noble metal. In one such embodiment, the noble metal is one such as, but not limited to Pd or Pt.

Material stack 120 may be fabricated by first performing a series of deposition operations. As an example, Figure 2 illustrates cross-sectional views of various operations in a method of fabricating a CBRAM element, in accordance with an embodiment of the present invention.

Referring to part (a) of Figure 2, a method of fabricating a conductive bridge random access memory (CBRAM) device includes forming an electrode material 102 (which ultimately becomes a first electrode layer 122) above a substrate 121. An electrolyte material 126 is then formed on the electrode material 102, as is depicted in part (b) of Figure 2, Referring to part (c) of Figure 2, a metal ion source layer 130 is formed on the electrolyte material 126. A second electrode layer 132 is then formed on the metal ion source layer 130.

Referring to part (d) of Figure 2, the material stack of part (c) of Figure 2 is patterned to form a first electrode layer 122, a patterned electrolyte layer, a metal ion source layer 130 and the second electrode layer 132. In one embodiment, the patterning is performed using a subtractive etching process, the resulting structure of which is described in greater detail below in

association with Figure 5A. In another embodiment, the patterning is performed using a damascene process, the resulting structure of which is described in greater detail below in association with Figure 6.

In accordance with an embodiment of the present invention, the patterned materials of the CBRAM element are exposed to a doping process. The doping process forms doped regions 129 at outermost ends of the electrolyte material 126 but not in a central portion of the electrolyte material 126. The doped electrolyte material 126 including the doped regions 129 are

collectively referred to a resistance switching layer 124 of a CBRAM element. In one

embodiment, the doping process is performed using a plasma-based doping process. In a specific such embodiment, the doping process provides a dopant species such as, but not limited to, B, C, N, O and F at the outermost ends of the electrolyte materi al 126.

Subsequent to exposing the CBRAM element to the doping process, a filament may be formed in the central portion of the electrolyte material of the resistance switching layer. For example, Figure 3 illustrates cross-sectional views of various operations in a method of forming a centralized filament in a CBRAM element, in accordance with an embodiment of the present invention. Part (a) of Figure 3 illustrates the CBRAM element of part (d) of Figure 2 following formation of a sidewall spacer 199 along the sidewalls of the CBRAM element. As such, in one embodiment, subsequent to exposing the CBRAM element to the doping process, the dielectric sidewall spacer 199 is formed laterally adjacent to and in contact with sidewalls of the second electrode layer 132, the metal ion source layer 130, the resistance switching layer 124, and the first electrode layer 122 of the CBRAM element. In one such embodiment, the sidewalls of the CBRAM element are formed during a subtractive etching of the materials of the CBRAM stack.

Part (b) of Figure 3 illustrates the CBRAM element of part (d) of Figure 2 following formation of a filament 128, e.g., by an electrical forming process described in greater detail below in association with Figures 9A and 9B. In an embodiment, as a result of the prior formation of the doped regions 129, only a single filament 128 is formed. In an embodiment, as a result of the prior formation of the doped regions 129, the filament 128 is centralized within the resistance switching layer 124. In an embodiment, as a result of the prior formation of the doped regions 129, only a single filament 128 is formed and the filament 128 is centralized within the resistance switching layer 124.

As depicted, in an embodiment, the dielectric sidewall spacer 199 is formed prior to forming the filament 128. In another embodiment, however, the dielectric sidewall spacer 199 is formed subsequent to forming the filament 128. In both such cases, in an embodiment, the dielectric sidewall spacer 199 is formed subsequent to forming the doped regions 129, such that the doped regions 129 can be formed by driving dopants into exposed edges of the electrolyte layer 126,

In another embodiment, a dielectric sidewall spacer is the source of dopants for the sidewalls of an electrolyte layer. In a specific such embodiment, the dielectric sidewall spacer includes dopant species selected from the group consisting of B, C, N, O and F. In this approach, at least a portion of the dopant species are driven from the dielectric sidewall spacer to form the doped regions 129 at outermost ends of the electrolyte material 126 but not in a central portion of the electrolyte material 126 of the resistance switching layer 124.

In an embodiment, the doped regions 129 at the outermost ends of the electrolyte material 126 of the resistive switching layer 124 have an approximately vertical leading edge profile, as is depicted in Figure IB and part (b) of Figure 3. As other possible examples of leading edge profiles, Figures 4A-4C illustrate cross-sectional views of CBRAM elements having engineered sidewalls with varied dopant profiles, in accordance with an embodiment of the present invention.

Referring to Figure 4A, in an embodiment, the doped regions 129A at the outermost ends of the electrolyte material 126A of the resistive switching layer 124A have a mid-dominant leading edge profile 402A. In one such embodiment, a filament 128 is formed between the mid- dominant leading edge profiles 402A. In another embodiment, the doped regions I 29B at the outermost ends of the electrolyte material 126B of the resistive switching layer 124B have an upper-dominant leading edge profile 402B. In one such embodiment, a filament 128 is formed between the upper-dominant leading edge profiles 402B. In another embodiment, the doped regions 129C at the outermost ends of the electrolyte material 126C of the resistive switching layer 124C have a lower-dominant leading edge profile 402C. In one such embodiment, a filament 128 is formed between the lower-dominant leading edge profiles 402C.

It is to be appreciated that a CBRAM element 120 may be fabricated on a conductive interconnect formed in an inter-layer dielectric (ILD) layer. As an example, Figure 5A illustrates a cross-sectional view of two CBRAM devices, in accordance with an embodiment of the present invention.

Referring to Figure 5 A, each of the CBRAM devices includes a conductive interconnect 506 disposed in an inter-layer dielectric (ILD) layer 504 disposed above a substrate 502. The ILD layer 506 may have an uppermost surface substantially co-planar with an uppermost surface of the conductive interconnect 506. A CBRAM: element 120 is disposed on each of the conductive interconnects 506. Each CBRAM element 120 may include the material layers described in association with Figure B, as is depicted in Figure 5 A.

In an embodiment, the conductive interconnect 506 includes a conductive line portion 508 and an underlying via portion 510, as is depicted in Figure 5 A. In another embodiment, the conductive interconnect is a conductive via. in one embodiment, the conductive interconnect includes a conductive fill material 514 surrounded by a barrier layer 512, which may include an upper barrier layer 516, as is depicted in Figure 5 A. In a specific such embodiment, the conductive fill material 514 but not the barrier layer 512 is recessed to form an opening in which the upper barrier layer 516 is then formed. In an embodiment, although depicted using different shading, the upper barrier layer 516 is composed of substantially the same material as barrier layer. In one such embodiment, the material includes tantalum nitride.

Referring again to Figure 5 A, in an embodiment, the materials of the memory (CBRAM) elements are patterned following a deposition process such as described in association with Figure 2. In one such embodiment, the material layers are patterned using a subtractive etching process. As depicted in Figure 5 A, a dielectric sidewali spacer 199 is laterally adjacent to and in contact with sidewali s of the patterned material layers of stacks 120, In one such embodiment, the dielectric sidewali spacer 199 formation includes conformal deposition of a dielectric material, such as a silicon nitride layer, and subsequent anisotropic etching to form the dielectric sidewali spacer 199. Thus, in one embodiment, the a dielectric sidewali spacer 199 is formed laterally adjacent to and in contact with sidewails of a first electrode layer 122, a resistance switching layer which includes an electrolyte material 126 having doped regions 129 at outermost ends of the electrolyte materi al 126, a metal ion source layer 130, and a second electrode layer 132.

Referring again to Figure 5 A, and as used throughout the present disclosure, in an embodiment, one or more interlayer dielectrics (ILDs), such as ILD layer 504, are included in a CBRAM device structure. Such ILD layers may be formed using dielectric materials known for their applicability in integrated circuit structures, such as low-k dielectric materials. Examples of dielectric materials that may be used include, but are not limited to, silicon dioxide (Si0 ₂ ), carbon doped oxide (CDO), silicon nitride, organic polymers such as perfluorocyclobutane or poiytetrafluoroethylene, fluorosilicate glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass. The ILD layers may include pores or air gaps to further reduce their dielectric constant. In cases where a stack of ILD layers is implemented, etch stop materials may be included as intervening dielectric layers between the ILD layers. Such etch stop layers may be composed of dielectric materials different from the interlayer dielectric material. In some embodiments, an etch stop layer includes a layer of a nitride of silicon (e.g., silicon nitride) or a layer of an oxide of silicon, or both, or a combination thereof. Other suitable materials may include carbon-based materials, such as silicon carbide. Alternatively, other etch stop layers known in the art may be used depending upon the particular implementation. The etch stop layers may be formed by CVD, PVD, or by other deposition methods.

Referring again to Figure 5 A, and as used throughout the present disclosure, in an embodiment, the metal lines (such as 508) and vias (such as 510) are composed of one or more metal or other conductive structures. A common example is the use of copper lines and structures that may or may not include barrier layers (such as Ta or TaN layers) between the copper and surrounding ILD material. As used herein, the term metal includes alloys, stacks, and other combinations of multiple metals. For example, the metal interconnect lines may include barrier layers, stacks of different metals or alloys, etc. The interconnect lines are also sometimes referred to in the arts as traces, wires, lines, metal, or simply interconnect.

Referring again to Figure 5 A, and as used throughout the present disclosure, in an embodiment, substrate 502 is a semiconductor substrate. In one implementation, the

semiconductor substrate may be a crystalline substrate formed using a bulk silicon or a silicon- on-insulator substructure. In other implementations, the semiconductor substrate may be formed using alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group !!i~V or group IV materials. Although a few examples of materials from which the substrate may be formed are described here, any material that may serve as a foundation upon which a semiconductor device m ay be built falls within the spirit and scope of the present invention.

Thus, it is to be appreciated that the layers and materials described in association with Figures IB or 5 A, and as used throughout the present disclosure, are typically formed on or above an underlying semiconductor substrate or structure, such as underlying device layer(s) of an integrated circuit. In an embodiment, an underlying semiconductor substrate 121 or 502 represents a general workpiece object used to manufacture integrated circuits. The

semiconductor substrate often includes a wafer or other piece of silicon or another semiconductor material. Suitable semiconductor substrates include, but are not limited to, single crystal silicon, polycrystalline silicon and silicon on insulator (SOI), as well as similar substrates formed of other semiconductor materials. The semiconductor substrate, depending on the stage of manufacture, often includes transistors, integrated circuitry, and the like. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in semiconductor substrates. In one embodiment, the illustrated structure depicted in Figure IB or 5A is fabricated on underlying transistor or other semiconductor device layer(s) formed in or above the substrate 121 or 502. In another embodiment, the illustrated stmctures depicted in Figure IB or 5A are fabricated on underlying lower level interconnect layers formed above the substrate 121 or 502, respectively.

In an aspect, CBRAM elements 120 may be formed on a common conductive line. As an example, Figure 5B illustrates a plan view of a pair of CBRAM elements integrated with a common line electrode, in accordance with an embodiment of the present invention.

Referring to Figure 5B, a conductive interconnect 550 housed in an ILD layer 504 includes two CBRAM stacks 120 thereon (e.g., stacks including layers described in association with Figures IB or 3 A). Each CBRAM stack 120 is disposed on a portion of an upper barrier layer 516 or a conductive fill material 514 of the conductive interconnect. The conductive interconnect in this example is a conductive line coupled to a first and second CBRAM stacks 120.

In another aspect, adjacent CBRAM elements 120 may be formed on respective conductive vias. As an example, Figure 5C illustrates a plan view of a pair of CBRAM elements integrated with discrete via electrodes, in accordance with an embodiment of the present invention.

Referring to Figure 5C, a pair of conductive vias 560 housed in an ILD layer 504 each has a respective CBRAM stack 20 thereon (e.g., stacks including layers described in association with Figures IB or 3 A). Each via is discrete and includes an exposed upper barrier layer 516 or conductive fill material 514, on which a corresponding CBRAM stack 120 is disposed.

The above described CBRAM material stacks may be fabricated through subtractive patterning of the layers of the CBRAM stack 120 materials, as is depicted in the examples above. In another aspect, however, the layers of a CBRAM element may be fabricated in a damascene- like fabrication scheme. As an example, Figure 6 illustrates a cross-sectional view of a conductive bridge random access memory (CBRAM) device fabricated using a damascene process, in accordance with an embodiment of the present invention.

Referring to Figure 6, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect 506 (e.g., one such interconnect described in association with Figure 5 A) disposed in a first inter-layer dielectric (ILD) layer 504 disposed above a substrate 502. A second ILD layer 604 is disposed above the first ILD layer 504. The second ILD layer 604 has an opening exposing the conductive interconnect 506 from a top down perspective. The opening has sidewalls, for example the sloped sidewalls depicted in Figure 6,

A CBRAM element 606 is disposed on the conductive interconnect 506. The CBRAM element 606 includes a first electrode layer 122, a resistance switching layer including an electrolyte material 126 having doped regions 129 at outermost ends of the electrolyte material 126, a metal ion source layer 130, and a second electrode layer 132. In one embodiment, the second ILD layer 604 is disposed directly on an uppermost surface 602 of the first ILD layer 504, as is depicted in Figure 6. In another embodiment, an etch stop layer is disposed between the first ILD layer 504 and the second ILD layer 604.

Referring again to Figure 6, in an embodiment, a damascene process is used in which the materials of the CBRAM element 606 are deposited conformal with an opening in a dielectric layer. The materials of the CBRAM element are then planarized, e.g., by chemical mechanical polishing, to form the CBRAM element 606. In one embodiment, following planarization, the planarized CBRAM stack is exposed to a doping process to form the doped sidewalls 129 of the electrolyte layer 126. Subsequent to the doping, a filament 128 may be formed, the filament 128 centralized in the electrolyte layer 126.

In another aspect, a conductive interconnect of an associated CBRAM element stack may be coupled to a drain region of an underlying select transistor disposed on a substrate. As an example, Figure 7 illustrates a cross-sectional view of a conductive bridge random access memory (CBRAM ) element coupled to a drain side of a transistor selector, in accordance with an embodiment of the present invention.

Referring to Figure 7, a memory structure 700 includes a transistor 702 disposed in or above an active region 704 of a semiconductor substrate 706. The transistor 702 includes a gate electrode 708 with source/drain regions 710 on either side of the gate electrode 708, and in active region 704 of substrate 706, In an embodiment, the source/drain region 710 on the left-hand side of Figure 7 is a source region, and the source/drain region 710 on the right-hand side of Figure 7 is a drain region. A CBRAM element 120 is coupled to the drain region of the transistor 702, but not to the source region of the transistor 702. The arrangement enables driving of the CBRAM element 120 by the drain side only. The CBRAM element 120 and portions of the transistor 702 may be included in an inter-layer dielectric (ILD) layer 750, as is depicted in Figure 7.

The CBRAM element 120 includes a first electrode layer 122, a resistance switching layer including an electrolyte material 126 having doped regions 129 at outermost ends of the electrolyte material 126, a metal ion source layer 130, and a second electrode layer 132, The CBRAM element 120 is, in an embodiment, included as an interrupting feature along a conductive drain contact 730, In one such embodiment, corresponding gate contact 734 and source contact 732 are not coupled to, or interrupted by the CBRAM element 120, as is depicted in Figure 7. It is to be appreciated that although the CBRAM element 120 is shown genetically along the drain contact 730 without a lateral reference, the actual layer in which the CBRAM element 120 is included may be viewed as an interconnect layer (e.g., Ml , M2, M3, M4, etc.) corresponding to a logic region in another area of the substrate 706. It is also to be appreciated that additional interconnect layer(s) may be formed on top of the structure 700 shown in Figure 7, e.g., using standard dual damascene process techniques that are well-known in the art.

In an embodiment, transistor 702 is a metal-oxide-semiconductor field-effect transistor

(MOSFET or simply MOS transistor), fabricated on a substrate. In various implementations of the invention, the MOS transistors described herein may be planar transistors, nonplanar transistors, or a combination of both. Nonplanar transistors include FinFET transistors such as double-gate transistors and tri-gate transistors, and wrap-around or all-around gate transistors such as nanoribbon and nanowire transistors.

In an embodiment, each MOS transistor includes a gate stack formed of at least two layers, a gate dielectric layer and a gate electrode layer. The gate dielectric layer may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide (Si0 ₂ ) and/or a high-k dielectric material. The high-k dielectric material may include elements such, as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric layer include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric layer to improve its quality when a high-k material is used.

The gate electrode layer of each MOS transistor is formed on the gate dielectric layer and may consist of at least one P-type workfunction metal or N-type workfunction metal, depending on whether the transistor is to be a PMOS or an NMOS transistor. In some implementations, the gate electrode layer may consist of a stack of two or more metal layers, where one or more metal layers are workfunction metal layers and at least one metal layer is a fill metal layer.

For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides, e.g., ruthenium oxide. A P-type metal layer will enable the formation of a PMOS gate electrode with a workfunction that is between about 4.9 eV and about 5,2 eV. For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals such as hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide. An N-type metal layer will enable the formation of an NMOS gate electrode with a workfunction that is between about 3.9 eV and about 4.2 eV.

In some implementations, the gate electrode may consist of a "LP'-shaped structure that includes a bottom portion substantially parallel to the surface of the substrate and two sidewall portions that are substantially perpendicular to the top surface of the substrate. In another implementation, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the substrate and does not include sidewall portions substantially perpendicular to the top surface of the substrate. In further implementations of the invention, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.

In some implementations of the invention, a pair of sidewall spacers 752 may be formed on opposing sides of the gate stack that bracket the gate stack. The sidewall spacers may be formed from a material such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In an alternate

implementation, a plurality of spacer pairs may be used, for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.

As is well known in the art, source and drain regions are formed within the substrate adjacent to the gate stack of each MOS transistor. The source and drain regions are generally formed using either an implantation/diffusion process or an etching deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the substrate to form the source and drain regions. An annealing process that activates the dopants and causes them to diffuse further into the substrate typically follows the ion implantation process. In the latter process, the substrate may first be etched to form recesses at the locations of the source and drain regions. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the source and drain regions. In some implementations, the source and drain regions may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some implementations the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In further embodiments, the source and drain regions may be formed using one or more alternate semiconductor materials such as germanium or a group DI-V material or alloy. And in further embodiments, one or more layers of metal and/or metal alloys may be used to form the source and drain regions.

To provide further context, integrating memory directly onto a microprocessor chip would be advantageous since it enables higher operation speeds compared to having physically separate logic and memory chips. Unfortunately, traditional charge-based memory technologies such as DRAM and A D Flash are now facing severe scalability issues related to increasingly- precise charge placement and sensing requirements. As such, embedding charge-based memory directly onto a high performance logic chip is not very attractive for future technology nodes, However, a memory technology that does have the potential to scale to much smaller geometries compared to traditional charge-based memories is conductive bridge random access memory (CBRAM), since it relies on resistivity rather than charge as the information carrier. However, in order to exploit the potential benefits of a high performance logic chip with embedded CBRAM memory, an appropriate integrated logic plus CBRAM structure and fabrication method is needed. Embodiments of the present invention include such structures and fabrication processes.

Relating to one or more embodiments described herein, it is to be appreciated that traditional DRAM memory is facing severe scaling issues and, so, other types of memory devices are being actively explored in the electronics industry. One future contender is CBRAM devices. Embodiments described herein include a fabrication method for embedding CBRAM bit cell arrays into a logic process technology. Embodiments described may be advantageous for processing schemes involving the fabrication of logic processors with embedded memory arrays.

In an aspect, a CBRAM element may be included in an integrated circuit in regions typically referred to as back end or back end of line (BEOL) layers of the integrated circuit. As examples, Figure 8A illustrates schematic views of several options for positioning a conductive bridge random access memory (CBRAM) element in an integrated circuit, in accordance with an embodiment of the present invention.

Referring to Figure 8 A, five examples (A)-(E) of a CBRAM cell situated above a second metal logic layer (M2) or higher are provided. In each case, a memory region 800 and a logic region 802 of an integrated circuit are depicted schematically. Each memory region 800 and logic region 802 is associated with a corresponding transistor (or group of transistors) 804 or 806, respectively. Stacks of metallization layers (as housed in encompassing dielectric layer or layers 897) include metal lines 808 and vias 810 that are generally alternating. Thus, all arrangements depicted include a CBRAM element disposed above a second metal line (M2) in the stack. The CBRAM element typically includes a resistance switching layer sandwiched between a bottom electrode and a top electrode, and may be formed in an opening of an insulating layer. The described arrangements can enable integration of both logic and memory on a same die versus stand-alone memory. Although depicted at a very high level conceptual view for the sake of illustrating general placement options, it is to be appreciated that, in accordance with an embodiment of the present invention, elements labeled CBRAM in Figure 8 A includes a stack of multiple layers such as those described above.

Referring again to Figure 8A, in a first example (A), a CBRAM element is fabricated on top of a unique via 850 intended for memory devices. In a second example (B), a CBRAM element is fabricated first and an upper unique via 860 contacts the CBRAM from above. In a third example (C), a CBRAM element has a top electrode with an increased thickness such that the CBRAM element occupies a full via depth, between metal lines. In a fourth example (D), a CBRAM element has a top electrode with an increased thickness such that the CBRAM element occupies a full metal line height. In a fifth example (E), a CBRAM element has a top electrode with an increased thickness such that the CBRAM element occupies a full interconnect level (via plus metal line). Accordingly, in an embodiment, a CBRAM element or an array of CBRAM elements can be embedded in a logic chip.

A CBRAM array may be embedded in a logic chip. As an example, Figure 8B illustrates a cross-sectional view of a logic region together with a conductive bridge random access memon,' (CBRAM) memory array integrated on a common substrate, in accordance with an embodiment of the present invention. Referring to Figure 8B, a structure 4000 includes a logic region 4020 and a CBRAM array region 4040.

Referring to the CBRAM array region 4040 of Figure 8B, in a first layer, metal 2 (M2) 4080 and via 1 (VI) 4100 structures are formed above a substrate 4060, The M2 4080 and VI 4100 structures are formed in an inter-layer dielectric layer 4120 disposed over an etch stop layer 4140. Referring again to the CBRAM array region 4040 of Figure 8B, in a second layer, a plurality of CBRAM stacks 120 is formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220. The plurality of CBRAM stacks 120 may be coupled to corresponding ones of the M2 4080 structures by a conductive layer 4240, as is depicted in Figure 8B. A dielectric spacer layer 199 may be formed on sidewalls of portions of the CBRAM stacks, as is also depicted in Figure 8B. Each of the CBRAM stacks 120 includes a first electrode layer 122, a resistance switching layer including an electrolyte material 126 having doped regions 129 at outermost ends of the electrolyte material 126, a metal ion source layer 130 and a second electrode layer 132. A top electrode 4340 may also be included, as is depicted in Figure 8B.

Referring again to the CBRAM array region 4040 of Figure 8B, in a third layer, an etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200. Metal 4 (M4) 4380 and via to memory 4400 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360. It is to be appreciated that additional interconnect layer(s) may be formed on top of the M4/via to memory layers of the CBRAM array region 4040 of Figure 8B, e.g., using standard dual damascene process techniques that are well-known in the art.

It is to be appreciated that although the CBRAM stacks may actually include numerous layers of very thin films, for the sake of simplicity the CBRAM stacks 120 are depicted as describe above. It is also to be appreciated that although in the illustrations the CBRAM stacks are shown embedded into a corresponding logic metal 3 (M3) layer, they may instead be embedded into some other interconnect layer (e.g., Ml, M2, M4, etc.)

Referring again to Figure 8B, in an embodiment, the conductive metal layer 4240 is a tantalum nitride (TaN) layer. In one embodiment, the conductive metal layer 4240 is referred to as a "thin via" layer. In an embodiment, the top electrode 4340 is composed of a material or stack of materials suitable for electrically contacting the CBRAM stack 120. In an embodiment, the top electrode 4340 is a topographically smooth electrode. In one such embodiment, the top electrode 4340 has a thickness suitable for good conductivity but has little to no columnar structure formation that would otherwise lead to a rough top surface. Such a topographically smooth electrode may be referred to as amorphous in structure. In an embodiment, the top electrode 4340 begins as a hardmask layer, such as a titanium nitride hardmask layer, used for patterning the CBRAM stack and is ultimately retained as a conductive contact.

Referring now to the logic region 4020 of Figure 8B, in the first layer, metal 2 (M2) 4500 and via 1 (VI) 4520 structures are formed in the inter-layer dielectric layer 4120 disposed over the etch stop layer 4140. In the second layer, the etch stop layer 4220 is disposed on the inter- layer dielectric layer 4120. Metal 3 (M3) 4540 and via 2 (V2) 4560 structures are formed in the inter-layer dielectric layer 4200 disposed over the etch stop layer 4220. In the third layer, the etch stop layer 4360 is disposed on the inter-layer dielectric layer 4200. Metal 4 (M4) 4580 and via 3 (V3) 4600 structures are formed in the inter-layer dielectric layer 4420 disposed over the etch stop layer 4360. It is to be appreciated that additional interconnect layer(s) may be formed on top of the M4/V3 layers of the logic region 4020 of Figure 8B, e.g., using standard dual damascene process techniques that are well-known in the art.

In another aspect, upon fabrication of a CBRAM element, the CBRAM may be subjected to an intentional one-time "break-down" process for filament formation in the resulting CBRAM device fabricated from the CBRAM memory element. To illustrate the above aspect, Figures 9A and 9B illustrate a schematic and corresponding I-V plot, respectively, demonstrating concepts involved with filament formation in a conductive bridge random access memory (CBRAM) element, in accordance with an embodiment of the present invention.

Referring to Figure 9A, a material stack 900 includes a bottom electrode (BE) 902, an electrolyte layer 904, a metal ion source layer 905, and a top electrode (TE) 906, Conductive bridge RAM cell filament formation begins with a forming (soft breakdown) operation (1) to provide a low resistance state (LRS). A first reset operation (2) is then performed to provide switching to a high resistance state (FIRS). A set operation (3) is then performed to return to the LRS. Performing operations (l)-(3) involves motion of metal ions and redox phenomena. Plot 910 of Figure 9B illustrates the I-V characteristics association with operations (1), (2) and (3) of Figure 9 A.

In another aspect, a CBRAM element or device may be a cationic-based electrolyte memory element. As an example, Figure 10 illustrates an operational schematic representing a changing of states for a CBRAM memory element, in accordance with an embodiment of the present invention. Referring to Figure 10, memory element 1000 may begin in a more conductive state (1), with a cationic-based electrolyte layer being in a more conductive state 1004A. An electrical pulse, such as a duration of a positive bias (2) may be applied to provide memory element 1000 in a less conductive state (3), with the cationic-based electrolyte layer being in a less conductive state 1004B. An electrical pulse, such as a duration of a negative bias (4) may be applied to again provide memory element 1000 having the more conductive state (1). Thus, electrical pulsing may be used to change resistance of the memory element 1000. Polarity applied is such as to attract active cations of in the memory layer to the intercalation electrode under negative bias.

As such, in an embodiment, a memory element includes a cationic-based electrolyte layer and associated metal ion source layer sandwiched between two electrodes. Resistivity of the cationic-based electrolyte layer in low field (when device is read) is, in some embodiments, can be as low as found typical of conductive films of metal compounds, e.g. TiAlN. For example, in a specific embodiment, the resistivity for such a layer is approximately in the range of 0.1 Ohm era - 10 kOhm cm when measured at low field (measured for the specific thickness used in the stack). Resistivity of the film is tuned depending in the memory element size to achieve final resistance value in the range compatible with fast read.

As an example of one approach, Figure 1 1 illustrates a schematic representation of resistance change in a CBRAM induced by changing the concentration of cation vacancies in the electrolyte layer, in accordance with an embodiment of the present invention.

Referring to Figure 1 1, a memor}' element 1 100 is shown as deposited (A). The memory element includes a cationic-based electrolyte layer 1 104 between a bottom electrode 1102 and a top electrode 1 106. in a specific example, the layer 1 104 is a lithium cobalt oxide layer, described in greater details below, and lithium atoms and lithium vacancies are distributed as shown in (A). Referring to (B) of Figure 1 1, upon application of a negative bias, the memory element 1 100 can be made more conductive. In that state, lithium atoms migrate to the top electrode 1106, while vacancies remain throughout the layer 1104. Referring to (C) of Figure 1 1, upon application of a positive bias to one of the electrodes, the memory element can be made less conductive. In that state, lithium atoms are distributed more evenly throughout layer 1104.

Accordingly, in an embodiment, effective composition (e.g., the location of lithium atoms (or cations) versus vacancies) of a cationic-based electrolyte layer is modified to change resistance of a memory element, in some embodiments due to stoichiometry-induced Mott transition. In a specific embodiment, an applied electrical field, which drives such compositional change during write operation, is tuned to values approximately in the range of Ie6-le7 V/'cm.

In an embodiment, referring again to Figure 11, the cationic-based electrolyte layer 1 104 is composed of a material suitable for cation-based mobility within the layer itself. In a specific exemplary embodiment, layer 1104 of Figure 1 1 part (A) is composed of lithium cobalt oxide (LiCoOi). Then, in part (B), the corresponding layer becomes lithium deficient (e.g.,

Li ₀ . ₇₅ CoO ₂ ) when a negative bias is applied and lithium atoms (e.g., as cations) migrate toward electrode 1 106. By contrast, in part (C), the corresponding layer becomes lithium rich (e.g., Li> ₀ .9 ₅ CoO ₂ ) when a positive bias is applied and lithium atoms (e.g., as cations) migrate away from electrode 106. In other embodiments, other suitable compositions with cationic conductivity include, but are not limited to, LiMn0 ₂ , Li ₄ Ti0 ₁₂ , LiNiOi, LiNbCh, l .u ^' vl L LiTiS ₂ (all of which are lithium atom or Li ⁺ mobility based), Na ?-aiumina (which is sodium atom or Na ^":" mobility based), or Agl, RbAg ₄ I ₅ , AgGeAsS ₃ (all of which are silver atom or Ag ⁺ mobility based). In general, these examples provide materials based on cation mobility or migration, which is typically much faster than anionic-based mobility or migration (e.g., for oxygen atoms or O ^2" anions). In an embodiment, referring again to Figure 11, one electrode (e.g., bottom electrode 1 02) in a memory element including a cationic electrolyte layer is a noble metal based electrode. In one embodiment, examples of suitable noble metals include, but are not limited to palladium (Pd) or platinum (Pt). In a specific embodiment, a memory stack includes a bottom electrode composed of an approximately 10 nanometer thick Pd layer.

In an embodiment, referring again to Figure 11, the other electrode (e.g., top electrode 1106) in a memory element including a cationic electrolyte layer is an "intercalation host" for migrating cations. The material of the top electrode is a host in a sense that the material is conductive with or without the presence of the migrating cations and is not substantially altered in the absence or presence of the migrating cations. In an exemplar)' embodiment, the top electrode is composed of a material such as, but not limited to, graphite, or metal chalcogenides such as disulfides (e.g., TaS ₂ ). Such materials are conductive as well as absorbing of cations such as Lr . This is in contrast to an electrode for an anionic based conductive oxide which may include a metal with a corresponding conductive oxide to accommodate migrating oxygen atoms or anions.

It is to be appreciated that a CBRAM material stack may be used to fabricate a memory bit cell. For example, Figure 12 illustrates a schematic of a memory bit cell 1200 which includes a conductive bridge random access memory (CBRAM) memory element 120, in accordance with an embodiment of the present invention. Such a CBRAM memory element may be suitable for manufacture on a substrate in common with logic regions of the substrate.

Referring to Figure 12, the CBRAM memory element 120 may include a first conductive electrode 122 with resistance switching layer 124 above the first conductive electrode 122. A second conductive electrode 132 is above the resistance switching layer 124. The second conductive electrode 132 may be electrically connected to a bit line 1232. The first conductive electrode 122 may be coupled with a transistor 1234. The transistor 1234 may be coupled with a wordline 1236 and a source line 1238 in a manner that will be understood to those skilled in the art. The memory bit cell 1200 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the memory bit cell 1200. It is to be appreciated that a plurality of the memory bit cells 1200 may be operably connected to one another to form a memory array, where the memory array can be incorporated into a non-volatile memory region of a substrate in common with a logic region. It is to be appreciated that the transistor 1234 may be connected to the second conductive electrode 132 or the first conductive electrode 122, although only the latter is shown. Figure 13 illustrates a block diagram of an electronic system 1300, in accordance with an embodiment of the present invention. The electronic system 1300 can correspond to, for example, a portable system, a computer system, a process control system, or any other system that utilizes a processor and an associated memory. The electronic system 1300 may include a microprocessor 1302 (having a processor 1304 and control unit 1306), a memory device 1308, and an input/output device 1310 (it is to be appreciated that the electronic system 1300 may have a plurality of processors, control units, memory device units and/or input/output devices in various embodiments). In one embodiment, the electronic system 1300 has a set of instructions that define operations which are to be performed on data by the processor 1304, as well as, other transactions between the processor 1304, the memory device 1308, and the input/output device 1310. The control unit 1306 coordinates the operations of the processor 1304, the memory device 1308 and the input/output device 1310 by cycling through a set of operations that cause instructions to be retrieved from the memory device 1308 and executed. The memory device 1308 can include a memory element as described in the present description. In an embodiment, the memory device 1308 is embedded in the microprocessor 1302, as depicted in Figure 13. In an embodiment, the processor 1304, or another component of electronic system 1300, includes an array of conductive bridge random access memory (CBRAM) devices, such as those described herein.

Figure 14 illustrates a computing device 1400 in accordance with one embodiment of the invention. The computing device 1400 houses a board 1402. The board 1402 may include a number of components, including but not limited to a processor 1404 and at least one

communication chip 1406. The processor 1404 is physically and electrically coupled to the board 1402. In some implementations the at least one communication chip 1406 is also physically and electrically coupled to the board 1402. In further implementations, the communication chip 1406 is part of the processsor 1404.

Depending on its applications, computing device 1400 may include other components that may or may not be physically and electrically coupled to the board 1402. These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, a graphics processor, a digital signal processor, a crypto processor, a chipset, an antenna, a display, a touchscreen display, a touchscreen controller, a battery, an audio codec, a video codec, a power amplifier, a global positioning system (GPS) device, a compass, an accelerometer, a gyroscope, a speaker, a camera, and a mass storage device (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth).

The communication chip 1406 enables wireless communications for the transfer of data to and from the computing device 1400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non- solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip 1406 may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.1 1 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev- DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 1400 may include a plurality of communication chips 1406. For instance, a first communication chip 1406 may be dedicated to shorter range wireless

communications such as Wi-Fi and Bluetooth and a second communication chip 1206 may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The processor 1404 of the computing device 1400 includes an integrated circuit die packaged within the processor 1404. In some implementations of embodiments of the invention, the integrated circuit die of the processor includes one or more arrays, such as conductive bridge random access memory (CBRAM) memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention. The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or mem or}'.

The communication chip 1406 also includes an integrated circuit die packaged within the communication chip 1406. In accordance with another implementation of an embodiment of the invention, the integrated circuit die of the communication chip includes conductive bridge random access memory (CBRAM) memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

In further implementations, another component housed within the computing device 1400 may contain a stand-alone integrated circuit memory die that includes one or more arrays, such as conductive bridge random access memory (CBRAM) memory arrays integrated into a logic processor, built in accordance with embodiments of the present invention.

In various implementations, the computing device 1400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra- mobile PC, a mobile phone, a desktop computer, a seiver, a printer, a scanner, a monitor, a set- top box, an entertainment control unit, a digital camera, a portable music player, or a digital

? 1 video recorder. In further implementations, the computing device 1400 may be any other electronic device that processes data.

Accordingly, one or more embodiments of the present invention relate generally to the fabrication of embedded microelectronic memory. The microelectronic memory may be non- volatile, where the memory can retain stored information even when not powered. One or more embodiments of the present invention relate to the fabrication of conductive bridge random access memory (CBRAM) memory arrays integrated into a logic processor. Such arrays may be used in an embedded non-volatile memory, either for its non-volatility, or as a replacement for embedded dynamic random access memory (eDRAM). For example, such an array may be used for 1T-1R memor or 2T-1R memory (R ^:; = resistor) at competitive cell sizes within a given technology node.

Figure 15 illustrates an interposer 1500 that includes one or more embodiments of the invention. The interposer 1500 is an intervening substrate used to bridge a first substrate 1502 to a second substrate 1504. The first substrate 1502 may be, for instance, an integrated circuit die, The second substrate 1 504 may be, for instance, a memory module, a computer motherboard, or another integrated circuit die. Generally, the purpose of an interposer 1500 is to spread a connection to a wider pitch or to reroute a connection to a different connection. For example, an interposer 1500 may couple an integrated circuit die to a ball grid array (BGA) 506 that can subsequently be coupled to the second substrate 1504. In some embodiments, the first and second substrates 1502/1504 are attached to opposing sides of the interposer 1500. In other embodiments, the first and second substrates 1502/1504 are attached to the same side of the interposer 1500. And in further embodiments, three or more substrates are interconnected by way of the interposer 1500.

The interposer 1500 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In further implementations, the interposer may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group HI-V and group IV materials.

The interposer may include metal interconnects 1508 and vias 1510, including but not limited to through-silicon vias (TSVs) 1512. The interposer 1500 may further include embedded devices 1514, including both passive and active devices. Such devices include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, and electrostatic discharge (ESD) devices. More complex devices such as radio- frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and MEMS devices may also be formed on the interposer 1500. In accordance with embodiments of the invention, apparatuses or processes disclosed herein may be used in the fabrication of interposer 1500,

Thus, embodiments of the present invention include approaches for fabricating conductive bridge random access memory (CBRAM) devices with engineered sidewalis for filament localization, and the resulting structures and devices, and the resulting structures and devices.

In an embodiment, a conductive bridge random access memory (CBRAM) device includes a conductive interconnect disposed in an inter-layer dielectric (ILD) layer disposed above a substrate. The CBRAM device also includes a CBRAM element disposed on the conductive interconnect. The CBRAM element includes a first electrode layer disposed on the uppermost surface of the conductive interconnect, A resistance switching layer is disposed on the first electrode layer. The resistance switching layer includes an electrolyte material having doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material. A metal ion source layer is disposed on the resistance switching layer. A second electrode layer is disposed on the metal ion source layer.

In one embodiment, the CBRAM: device further includes a single filament disposed in the central portion of the electrolyte material.

In one embodiment, the doped regions at the outermost ends of the electrolyte material have an approximately vertical leading edge profile.

In one embodiment, the doped regions at the outermost ends of the electrolyte material have a mid-dominant leading edge profile.

In one embodiment, the doped regions at the outermost ends of the electrolyte material have a lower-dominant leading edge profile.

In one embodiment, the doped regions at the outermost ends of the electrolyte material have an upper-dominant leading edge profile.

In one embodiment, the doped regions at the outermost ends of the electrolyte material have a depth into the outermost ends of the electrolyte material approximately equal to a thickness of the resistance switching layer.

In one embodiment, the thickness of the resistance switching layer is approximately in the range of 1-2 nanometers.

In one embodiment, the metal ion source layer includes a metal species selected from the group consisting of copper, silver, and lithium.

In one embodiment, the doped regions include dopant species selected from the group consisting of B, C, N, O and F. In one embodiment, the electrolyte material is a chalcogenide material or a metal oxide material.

In one embodiment, the CBRAM device further includes a dielectric sidewall spacer laterally adjacent to and in contact with sidewails of the second electrode layer, the metal ion source layer, the resistance switching layer, and the first electrode layer of the CBRAM element.

In one embodiment, the dielectric sidewall spacer includes dopant species selected from the group consisting of B, C, N, O and F.

In one embodiment, the second electrode layer, the metal ion source layer, the resistance switching layer, and the first electrode layer of the CBRAM element are disposed at a bottom of and along sidewails of an opening disposed in a second ILD layer disposed above the ILD layer.

In one embodiment, the conductive interconnect is a conductive line further coupled to a second CBRAM element.

In one embodiment, the conductive interconnect is a conductive via.

In one embodiment, the conductive interconnect is coupled to a drain region of an underlying select transistor disposed in or above the substrate.

In an embodiment a method of fabricating a conductive bridge random access memory (CBRAM) device includes forming a conductive interconnect in an inter-layer dielectric (ILD) layer formed above a substrate. The method also includes forming a first electrode layer on the conductive interconnect. The method also includes forming a resistance switching layer on the first electrode layer, the resistance switching layer including an electrolyte material. The method also includes forming a metal ion source layer disposed on the resistance switching layer. The method also includes forming a second electrode layer on the metal ion source layer. The method also includes patterning the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer to form a CBRAM element. The method also includes exposing the CBRAM element to a doping process to form doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material of the resistance switching layer.

In one embodiment, exposing the CBRAM element to the doping process includes plasma doping to provide dopant species selected from the group consisting of B, C, N, O and F the at outermost ends of the electrolyte material.

In one embodiment, patterning the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer to form the CBRAM element includes subtract! ve etching the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer. In one embodiment, the method further includes, subsequent to exposing the CBRAM element to the doping process, forming a dielectric sidewall spacer laterally adjacent to and in contact with sidewalls of the second electrode layer, the metal ion source layer, the resistance switching layer, and the first electrode layer of the CBRAM element. The sidewalls are formed during the subtractive etching.

In one embodiment, patterning the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer to form the CBRAM element includes planarizing the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer within an opening formed in a second ILD layer formed above the ILD layer.

In one embodiment, the method further includes, subsequent to exposing the CBRAM element to the doping process, forming a filament in the central portion of the electrolyte material of the resistance switching layer.

In an embodiment, a method of fabricating a conductive bridge random access memory (CBRAM) device includes forming a conductive interconnect in an inter-layer dielectric (ILD) layer formed above a substrate. The method also includes forming a first electrode layer on the conductive interconnect. The method also includes forming a resistance switching layer on the first electrode layer. The resistance switching layer includes an electrolyte material. The method also includes forming a metal ion source layer on the resistance switching layer. The method also includes forming a second electrode layer on the metal ion source layer. The method also includes subtractive etching the first electrode layer, the resistance switching layer, the metal ion source layer and the second electrode layer to form a CBRAM element. The method also includes forming a dielectric sidewall spacer laterally adjacent to and in contact with sidewalls of the second electrode layer, the metal ion source layer, the resistance switching layer, and the first electrode layer of the CBRAM element, the sidewalls formed during the subtractive etching, and the dielectric sidewall spacer including dopant species selected from the group consisting of B, C, N, O and F. The method also includes driving at least a portion of the dopant species from the dielectric sidewall spacer to form doped regions at outermost ends of the electrolyte material but not in a central portion of the electrolyte material of the resistance switching layer.

In one embodiment, the method further includes, subsequent to driving the dopant species from the dielectric sidewall spacer, forming a filament in the central portion of the electrolyte material of the resistance switching layer.

? 5