CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS

Title:

CONFINED SPACERS FOR DOUBLE GATE TRANSISTOR SEMICONDUCTOR FABRICATION PROCESS

Document Type and Number:

WIPO Patent Application WO2005045892

Kind Code:

A3

Abstract:

A semiconductor fabrication process includes forming a silicon fin overlying a substrate. A gate dielectric formed on primary faces of the fin. A gate electrode is formed over at least two faces of the fin. Dielectric spacers are then selectively formed in close proximity and confined to the sidewalls of the gate electrode thereby leaving a majority of the primary fin faces exposed. Thereafter a silicide is formed on the primary fin faces. The forming of the gate electrode in one embodiment includes depositing polysilicon over the fin and substrate, depositing a capping layer over the polysilicon, patterning photoresist over the capping layer and etching through the capping layer.

Inventors:

MATHEW LEO (US)
MORA RODE R (US)
NGUYEN BICH-YEN (US)
STEPHENS TAB A (US)
VANDOOREN ANNE M (FR)

Application Number:

PCT/US2004/035349

Publication Date:

September 15, 2005

Filing Date:

October 20, 2004

Export Citation:

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Assignee:

FREESCALE SEMICONDUCTOR INC (US)
MATHEW LEO (US)
MORA RODE R (US)
NGUYEN BICH-YEN (US)
STEPHENS TAB A (US)
VANDOOREN ANNE M (FR)

International Classes:

H01L21/336; H01L29/423; H01L29/49; H01L29/786; H01L21/8234; (IPC1-7): H01L21/00; H01L21/84; H01L21/3205; H01L21/4763

Foreign References:

US6413802B1	2002-07-02
US6657252B2	2003-12-02
US6635909B2	2003-10-21

Other References: