Title:
CONNECTING STRUCTURE AND CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2018/056200
Kind Code:
A1
Abstract:
The present invention addresses the problem of providing a connecting structure or similar that can minimize a decrease in a wireable region of a substrate while reducing the effect of stubs of a pair of vias on the output of a capacitor that is connected to said vias. In order to solve this problem, this connecting structure comprises: a first conductor that passes through a substrate and is provided with a first input/output section; a second conductor that passes through the substrate and is provided with a second input/output section; a first capacitor, one terminal of which being connected to a terminal of the first conductor that is on a first surface of the substrate, the other terminal of which being connected to a terminal of the second conductor that is on the first surface of the substrate; and a second capacitor or a resistor, one terminal of which being connected to a terminal of the first conductor that is on a second surface of the substrate, another terminal of which that is not connected to the one terminal being connected to a terminal of the second conductor that is on the second surface, wherein the first input/output section is provided to a portion of a side section of the first conductor, and/or the second input/output section is provided to a portion of a side section of the second conductor.
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Inventors:
UEMURA AYAKO (JP)
KASHIWAKURA KAZUHIRO (JP)
KASHIWAKURA KAZUHIRO (JP)
Application Number:
PCT/JP2017/033425
Publication Date:
March 29, 2018
Filing Date:
September 15, 2017
Export Citation:
Assignee:
NEC CORP (JP)
International Classes:
H05K3/46
Foreign References:
JP2015225960A | 2015-12-14 | |||
JP2007250818A | 2007-09-27 | |||
JP2014229865A | 2014-12-08 | |||
JP2007317716A | 2007-12-06 | |||
JP2011014759A | 2011-01-20 | |||
JP2016018837A | 2016-02-01 |
Attorney, Agent or Firm:
SHIMOSAKA Naoki (JP)
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