BACKGROUND OF THE INVENTION

[0001] The invention relates to DC converters and particularly to a half-bridge switched-mode, current-mode-controlled DC converters.

[0002] A direct current converter or a DC-DC converter is a circuit converting a direct-current voltage (DC) from one voltage level to another. A half-bridge switched-mode DC-DC converter operating in the switched-mode transfers energy by means of windings magnetically coupled to each other. This topology requires not only a transformer transferring energy in an isolated manner but also an inductance serving as energy storage. Controlling the duty cycle of the charging voltage, i.e. the ratio of on/off-times, according to the feedback output voltage level by pulse width modulation, for instance, allows the amount of energy transferred to the output and thus the output voltage to be controlled. DC converters can be divided into two basic types according to the control: voltage-mode-controlled and current-mode-controlled converters. In a voltage-mode-controlled converter, only the output voltage is monitored. US 4347558 discloses a balancing circuit for a voltage-mode-controlled half bridge, which measures, in addition to the output voltage, the voltages across the capacitors and generates for the pulse-width modulator a signal that compensates for the imbalance of the voltages by controlling the on/off-times of both half-bridge switches.

[0003] In a current-mode-controlled converter, both the output voltage and the primary voltage are monitored. Figure 1 shows, as an example, an illustrative circuit diagram of a current-mode-controlled, half- bridge switched-mode DC converter. The half-bridge converter comprises supply buses and conductors of a DC input voltage V _b , between which there is a series connection of a pair of capacitors C1, C2 as well as a series connection of a pair of switches M1 , M2. A primary winding N1 of a power transformer T is connected between a connection node A between the capacitors C1 , C2 and a connection node B between the switches M1 , M2. The two-part secondary winding N1 , N2 of the transformer T has a grounded centre tap and end terminals, which are connected to an output coil L4 via diode rectifiers D1 and D2, respectively, the output coil being followed by a smoothing capacitor C3 and a load resistor RLOAD- A DC output voltage V _O uτ appears across the capacitor C3.

[0004] The operation of the switches M1 , M2 is controlled by means of a current-mode controller 10. The current passing through the primary winding N1 of the transformer T is measured with a measuring transformer K1 through which the primary current of the primary winding passes. The generated measurement signal of the secondary winding of the measuring transformer K1 is applied to a current-mode controller 10. The current-mode controller 10 alternately switches the switches M1, M2 ON by means of control signals ml and m2. Switching the switches M1 , M2 OFF takes place when the measured primary current reaches a threshold value adjusted according to the information on the deviation of the secondary voltage from the desired value. This information is obtained via an output voltage feedback 11 , for instance. In this way, the level of the output voltage VOUT can be adjusted as desired.

[0005] The balancing problem of a half bridge, which is generally known, arises even from a small error or disturbance in the primary current measurement. If, for example, when the switch M2 is on, the primary current measurement contains a disturbance which increases the time (t _on ) of the conducting state of the switch M2, this causes the voltage V _m of the midpoint A of the capacitors C1 , C2 to drift slightly downwards. During the following conducting cycle of the switch M2, the voltage V _m of the midpoint A drifts further downwards even if there were no longer a disturbance in the current measurement, because increasing the current to the current limit requires more time, and thereby electric charge is discharged from the midpoint A. A change ΔU in the voltage at the midpoint A affects electric charge Q as follows:

Q _= c * ΔU = C * i * Δt, where

C - capacitance

Q = electric charge of the capacitance

ΔU = change in the voltage of the capacitance i = primary current

Δt = change in the conducting time of the switch.

[0006] A short extension Δt of the conducting time (duty cycle of the signal m2) of the switch M2 thus causes the voltage at the midpoint A to decrease by the value ΔU, whereby during the next conducting cycle of the switch M2, again more time is needed to reach the current limit of the primary current measurement.

[0007] Due to this balancing problem, a half-bridge switched-mode DC converter was long used only in a voltage-mode-controlled manner, so that the feedback was based solely on measurement of the output voltage. After that, various half-bridge switched-mode, current-mode-controlled DC converters have been introduced with attempts to solve the balancing problem. A drawback with all of these is, however, the large number of components, which increases the material and work costs of the DC converter.

[0008] US 6014326 discloses a half bridge where the primary side of the power transformer is divided into a power winding and a balance winding having the same number of turns. The centre tap between the power winding and the balance winding forms the midpoint of the half bridge. One end of the balance winding is connected, via balancing diodes, to a supply voltage Vj _n and the ground. As a result, the midpoint is forced to a voltage Vj _n /2 because while the voltage of the midpoint is drifting away from the value VJ _Π /2, there passes through the balance winding a current which compensates for the drift when one of the balancing diodes conducts and charges either of the capacitors of the half bridge, whereby the voltage of the midpoint moves towards the value V _in /2. Current-mode control comprises a current-measuring transformer which measures both the current of the power winding and the current of the balance winding with different measuring windings and generates a combined current measurement signal where the measured current of the balance winding of the power winding has been subtracted from the measured current of the power winding. This solution increases not only the material and work costs of the converter but also, to some extent, the stray inductance and power consumption of the power transformer and reduces the coupling factor because the balance winding is provided between the primary and the secondary winding.

[0009] US 5189601 discloses a balancing circuit of a half bridge, which is aimed at eliminating the balance winding. The current-mode controller measures the current passing through the conductive switch and controls the switch to be non-conductive when the current reaches a given threshold level. Then, the controller generates a control signal that switches a second switch conductive. The pulse width of this second control signal is the same as the time during which the first switch was conductive. This arrangement keeps the voltage of the midpoint constant without a balance winding. A drawback is the complex current-mode controller.

BRIEF DESCRIPTION OF THE INVENTION

[0010] An object of the invention is a novel balancing method and balancing circuit with which a balance winding can be avoided with a small number of components. The object of the invention is achieved with a method and a circuit which are characterized by what is stated in the independent claims. Preferred embodiments of the invention are disclosed in the dependent claims.

[0011] An aspect of the invention is a control method for a half- bridge switched-mode DC converter, comprising measuring a primary current of a main transformer of a current-mode-controlled half bridge and controlling conduction times of switches on a primary side of the half bridge on the basis of a voltage feedback from a secondary side and the measured primary current. In the measurement of the primary current, a correction error is caused which is directly proportional to a deviation of a half voltage of the half bridge from half of an input voltage of the half bridge and which affects conduction times of the switches on the primary side in such a way that the deviation of the half voltage is compensated for. This can be achieved with a small number of components, and no components need to be added to the main circuit. Instead, measurement of the primary current is influenced. The invention does not necessarily require any changes in the actual controller of the switches, such as in a pulse width modulator, to which the measured primary current is fed.

[0012] In accordance with an embodiment of the invention, a correction error is caused to said primary current measurement during a conduction state of only one switch. Control of the other switch takes place by means of uncorrected primary current measurement. This is possible because the voltage feedback compensates for the change in the output voltage. This simplifies the balancing and decreases the number of components even further.

[0013] In accordance with an embodiment of the invention, the deviation of the half voltage of the half bridge is measured on only one side of the half bridge, for example across the upper capacitor. This simplifies the balancing and decreases the number of components even further. [0014] In accordance with an embodiment of the invention, a correction error is caused to the primary current measurement by increasing or decreasing the measured primary current in proportion to the deviation of the half voltage. In accordance with an embodiment of the invention, the deviation of the half voltage of the half bridge is measured by obtaining a difference between the current proportional to the half voltage and a current proportional to the input voltage, said difference being added to said primary current. The conduction time of the switch ends when the corrected primary current measured reaches a limit value formed on the basis of the voltage feedback from the secondary side.

[0015] An aspect of the invention is a control circuit for a half-bridge switched-mode DC converter, comprising means for measuring a primary current of a main transformer of a current-mode-controlled half bridge, and control means for controlling conduction times of switches on a primary side of the current-mode-controlled half bridge on the basis of a voltage feedback from a secondary side and the measured primary current. The control circuit further comprises correction means with which a correction is caused to the primary current measurement, the correction being proportional to a deviation of a half voltage of the half bridge from half of an input voltage of the half bridge and affecting the conduction times of the switches on the primary side in such a way that the deviation of the half voltage is compensated for.

[0016] In an embodiment of the invention, the correction means comprise means for generating a correction current proportional to the deviation of the half voltage from half of the input voltage, and means for adding the correction current to the measured primary current. The control means are arranged to control the switch to transit from a conductive to a non- conductive state when the sum of the correction current and the measured primary current reaches a limit value formed on the basis of a voltage feedback from the secondary side. In preferred embodiments of the invention, the control means comprises a pulse width modulator.

[0017] In an embodiment of the invention, the means for generating the differential current comprise a current mirror in which a collector current Ib of a second transistor stage connected to the input voltage via a resistor is determined to be equal to a collector current Im of a first transistor stage connected to the half voltage via a resistor, whereby a differential current Im - Ib is generated at an output of the current mirror. [0018] In accordance with an embodiment of the invention, said means for adding the correction current are arranged to add the correction current to the measured primary current to correct the conduction time of only one of the switches on the primary side.

[0019] In an embodiment of the invention, the means for adding the correction current comprise reverse-coupled transistors and controlled to be conductive simultaneously with the other switch on the primary side.

[0020] A feature of the invention is a half-bridge switched-mode current-controlled converter, comprising a first switch and a second switch connected in series between the input voltage terminals, whereby there is a first connection node between the switches; a first capacitor and a second capacitor connected in series between the input voltage terminals, whereby there is a second connection node between the capacitors; a power transformer with a primary winding connected between the first and the second connection node, and a secondary winding provided with a centre tap; a secondary circuit for generating an output voltage and a voltage feedback; and a control circuit according to any of the embodiments of the invention.

BRIEF DESCRIPTION OF THE FIGURES

[0021] The invention will now be described in more detail in connection with exemplary embodiments, referring to the attached drawings, of which:

Figure 1 shows, as an example, an illustrative circuit diagram of a current-mode-controlled half-bridge switched-mode DC converter;

Figure 2 shows an illustrative circuit diagram of a current-mode controlled half-bridge switched-mode DC converter, to which a balancing circuit according to an exemplary embodiment is applied; and

Figure 3 is a circuit diagram showing an implementation according to an exemplary embodiment of the invention for blocks B1 and B2 in the DC converter of Figure 2. DESCRIPTION OF EXEMPLARY EMBODIMENTS OF THE INVENTION

[0022] Figure 2 shows, as an example, an illustrative circuit diagram of a current-mode-controlled half-bridge switched-mode DC converter, to which the present invention is applied. The converter comprises supply buses or conductors of a DC input voltage V _b , between which there is a series connection of a pair of capacitors C1 , C2 as well as a series connection of a pair of semiconductor switches M1, M2. The semiconductor switches M1 and M2 may be MOFSET transistors, for example, and they are identical with each other. The capacitors C1 and C3 are also identical with each other. A primary winding N1 of a power transformer T is connected between a connection node A between the capacitors C1 , C2 and a connection node B between the switches M1 , M2. A two-part secondary winding N1 , N2 of a transformer T has a grounded centre tap and end terminals connected to the output stage of the converter. Implementation of the output stage is not relevant to the invention, and this stage can be implemented with any appropriate circuit structure. In an embodiment of the invention, the output stage may be implemented in the manner according to Figure 1 , whereby the end terminals of the secondary windings N1 , N2 are connected to an output coil L4 via diode rectifiers D1 and D2, respectively, the output coil being followed by a smoothing capacitor C3 and a load resistor RLOAD- A DC output voltage V _O uτ appears across the capacitor C3. The output stage 21 also generates a feedback signal V _F representing the secondary voltage or the output voltage VOUT or an error thereof (e.g. a measuring voltage representing the output voltage).

[0023] The primary winding of a measuring transformer K1 is connected in series with the primary winding N1 of the transformer T, between nodes A and B, the primary current of the transformer T passing through the primary winding of the measuring transformer. The measurement signal generated in the secondary winding of the measuring transformer K, i.e. the secondary voltage or current, is fed to a block B4 of the current-mode controller. Block B4 is, for instance, a full-wave rectifier that rectifies the secondary current of the measuring transformer K. The output of block B4 may be connected via a resistor R4 to the ground and via a resistor R1 to a node CS connected to one input of a block B3. A capacitor C4 is connected between node CS and the ground. The rectified output current of block B4 generates a voltage V _R4 across the resistor R4, the voltage being proportional to the primary current of the transformer T. This voltage V _R4 , in turn, charges the capacitor C4 via the resistor R1 by means of a measuring current lcs also proportional to the primary current of the transformer T.

[0024] Block B3 is a controller which is based on pulse width modulation (PWM) and which controls the switches M1 and M2 connected to the half bridge. One of the inputs of block B3 is a feedback signal V _F . In the exemplary embodiment of Figure 2, control of the switches takes place via a pulse transformer DT. However, the control may also be implemented in other ways, such as by means of optical isolators. In the exemplary embodiment, the output Out A of block B3 is connected to the control input of a block B2 and to the (+) terminal of the primary winding N1 of the pulse transformer DT. The second output Out B of block B3 is connected to the (-) terminal of the primary winding N1 of the pulse transformer DT. The transformer DT has a pair of secondary windings N2 and N3 in a reversed polarity configuration. The (+) terminal of the secondary winding N2 is connected to the gate of the switch M1 , and the (-) terminal is connected to node B. The (-) terminal of the secondary winding N3 is connected to the gate of the switch M2, the (+) terminal being connected to the ground terminal of the switch M2.

[0025] Block B controls the switches M1 and M2 alternately to conductive ON-state in such a way that they are timed at a given frequency, and controls the ON-time of the switches, i.e. the duty cycle, with pulse width modulation. Both switches M1 and M2 are in a non-conductive state (OFF) when both control outputs Out A and Out B of block B3 are low (e.g. ground potential). The switch M1 is controlled to be in a conductive state (ON) when the control output Out A transits high (e.g. input potential Vb) while the other control output Out B is low. When the measurement voltage Vcs that is proportional to the current of the primary winding N1 of the transformer T exceeds a threshold level determined by the feedback VF, in other words when the primary current has reached a given limit value, the control output Out A of block B3 transits low and the switch M1 is controlled to be OFF. Correspondingly, the switch M2 is controlled to be ON when the control output Out B transits high (e.g. ground potential Vb) while the control output Out A is low. When the measuring voltage Vcs that is proportional to the current of the primary winding N1 of the transformer T exceeds a threshold level determined by the feedback VF, in other words when the primary current has reached a given limit value, the control output Out B of block B3 transits low and the switch M2 is controlled to be OFF. [0026] As noted earlier, the generally known balancing problem of a half bridge arises from even a small error or disturbance in the measurement of the primary current. If, for example, when the switch M2 is ON, the primary current measurement contains a disturbance which increases the time (t _on ) of the ON-state of the switch M2, this causes the voltage V _m of the midpoint A of the capacitors C1 , C2 to drift slightly downwards. During the following ON- cycle of the switch M2, the voltage V _m of the midpoint A drifts further downwards even if there were no longer a disturbance in the current measurement, because increasing the current to the current limit requires more time, and thereby electric charge is discharged from the midpoint A.

[0027] In accordance with an embodiment of the invention, the current-mode-controlled half bridge is balanced by causing to the measurement of the primary current of the transformer T a deliberate "counter- disturbance" or error that is directly proportional to the deviation of the voltage Vm from half Vb/2 of the input voltage Vb. In the primary embodiment of the invention, the ON-time of only one of the switches M1 and M2 is corrected. The following describes an example of how the time during which the switch M1 is ON can be corrected. Alternatively, correction of the ON-time of the switch M2 can be implemented with the same principle.

[0028] As noted earlier, the capacitors C1 and C2 are connected in series between the input voltage Vin = Vb and the ground (or other potential). In an ideal situation, the voltage Vm of the connection node A between the capacitors C1 and C2 is half of the input voltage, i.e. Vm = Vb/2. The input voltage Vb is connected to one input of block B1 via a resistor R2, and the voltage Vm is connected to the other input of block B2 via the resistor R3, whereby a current Ib = Vb/R2 proportional to the input voltage Vb passes through the resistor R2, and a current Im = Vm/R3 proportional to the voltage Vm passes through the resistor R3. Block B1 forms the difference Im - Ib between the currents. In an exemplary embodiment of the invention, the resistors R2 and R3 are selected in such a way that R2 = 2 * R3, whereby in a balance situation Im - Ib = 0 because Vb = 2 ^* Vm.

[0029] Figure 3 shows an example of implementing blocks B1 and B2. Block B1 is, in its simplest form, a mere current mirror. Discrete transistors (Q1, Q2) or a special current mirror (matched double transistor) may be used in the current mirror. In Figure 3, block B1 comprises NPN bipolar transistors Q1 and Q2 connected as a current mirror (emitters and bases are interconnected and the collector of the transistor Q1 is connected to the base), the collectors of the transistors (the inputs of block B1) being connected to the resistors R3 and R2, respectively. The output (current Im - Ib) of block B2 is taken from the collector of the transistor Q2. In the current mirror, the collector current of one transistor may be determined to correspond to the collector current of the other transistor (= mirroring). For the purpose of the invention, the current Ib (in the example the collector current of the transistor Q2) may be determined to be equal to Im = Vm/R3 (in the example the collector current of the transistor Q1). The base emitter voltages of the transistors may be ignored because they do not, due to their low level, affect the balancing currents (0.6 V « Vm).

[0030] The current mirror of block B1 operates as follows. Let us define the voltage change at the connection node A of the capacitors C1 and C2 as ΔU. Thus, the differential current Im - Ib can be presented as follows:

Im = Vm/R3 = (Vb/2 + ΔU)/R3

Ib = Vb/R2 = (Vb/2 * R3)

Im - Ib = ΔU/R3.

[0031] If ΔU is positive (Vm > Vb/2), the current Im - Ib output by block B1 is positive. If, on the other hand, ΔU is negative (Vm < Vb/2), the current Im - Ib output by block B1 is negative, in other words block B1 takes current from block B2 and/or from node CS.

[0032] The differential current Im - Ib is connected to node CS with the switching block B2 controlled by the control output Out A. Block B3 may be implemented, in its simplest form, with one semiconductor switch, such as an N-channel FET. Its parasitic capacitances (Cin, Cos) may be too high, however, in which case the control (OUT/PWM) of FET may disturb the balancing. In the example of Figure 3, block B2 is implemented with reverse- coupled NPN bipolar transistors Q3 and Q4, with which improved operation is achieved. The collector, base and emitter of the transistor Q3 are connected to the emitter, base and collector of the transistor Q4, respectively. Control OutA/PWM is connected to the bases of the transistors via a resistor R5. When OuWPWM is high, both transistors Q3 and Q4 are conductive but in opposite directions. When positive, the differential current Im - Ib passes from the output of block B1 through the transistor Q3 to node CS. When negative, the differential current Im - Ib passes from node CS through the transistor Q4 to the output of block B1.

[0033] In other words, the connecting block B2 adds the differential current Im - Ib to node CS when the control output Out A transits high and the switch M1 is switched ON. Thus, the capacitor C4 is charged with the sum of the measuring current lcs and the differential current Im - Ib. If the voltage Vm is higher than Vb/2, the differential current Im - Ib is positive, whereby it increases the summation current charging the capacitor C4. Then, the measuring voltage Vcs at node CS reaches the threshold level determined by the feedback V _F , i.e. the limit value set for the primary current, somewhat earlier than without correction, and the ON-time of the switch M1 becomes thus shorter. This results in the charge provided at the midpoint of the capacitors C1 and C2 being lower, so the voltage Vm increases less than without correction. Correspondingly, if the voltage Vm is lower than Vb/2, the differential current Im - Ib is negative, whereby it decreases the summation current charging the capacitor C4. Thus, the measuring current V _C s at node CS reaches the threshold level determined by the feedback VF, i.e. the limit value set for the primary current, somewhat later than without correction, and the ON time of the switch M1 becomes thus longer. This results in the charge brought to the midpoint of the capacitors C1 and C2 being higher, so the voltage Vm increases more than without correction.

[0034] In the exemplary embodiment of the invention, the differential current Im - Ib is not connected to node CS when the control output Out A is low and the switch M2 is ON. This does not cause a change in the output voltage Vout because when the voltage Vm is corrected, the feedback of the output voltage Vout reacts to the correction in the same direction: if, for example the ON-time of the switch M1 is shortened, the secondary voltage of the transformer T tends to decrease, whereby the threshold level determined by the feedback VF gets higher and the switch M2 (which is not affected by the correction according to the invention) will be ON slightly longer, correcting the change.

[0035] The invention and its embodiments are not restricted to the above examples but may vary within the scope of the claims.