BACKGROUND

[0001] A mixed memory medium contains multiple types of memory on the medium. For example, non-volatile dual-inline memory modules ("NVD! ") can contain a dynamic random access memory ("DRAM") component and a non-volatile ("NV") flash memory component. A mixed memory medium can contain a controller to manage the medium. For example, an NVD! IVS can have a microcontroller having a control program to backup data from the DRAM component to the NV flash memory component when a system power event occurs. A common communication mechanism between the controller of a mixed memory medium and a system processor resource executing an operating system is through an inter-integrated circuit bus ("I2C") bus.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Figure 1 is a block diagram depicting an example system for updating a control program consistent with disclosed examples.

[0003] Figure 2 is a block diagram depicting an example apparatus that is able to update a control program consistent with disclosed examples.

[0004] Figure 3 depicts an example system in which various example apparatus 300 can be implemented consistent with disclosed examples for updating a control program.

[0005] Figures 4 and 5 are flow diagrams depicting example methods for updating a control program of a microcontroller consistent with disclosed examples. DETAILED DESCRIPTION

[0006] In the following description and figures, some example implementations of apparatus, systems, and/or methods for updating a control program (e.g., firmware) are described. A controller generally has a control program that commonly resides in an NV storage medium. A control program, as used herein, represents executable instructions (e.g., program code) that enables the functionality of the device on which the controller resides. Control programs are commonly updated to correct errors and provide new functionalities, such as compatibility with developed format types. Control programs can become large and complex. Large updates to the control program can take up to an hour when transferred over the general communication bus (e.g., an I2C bus).

[0007] Various examples described below relate to transferring a control program through a memory component of the mixed memory medium (e.g., the DRAM

component of an NVDIMM) rather than the communication interface (e.g., the I2C bus). The controller of the memory medium can be programmed to identify when and where a control program image (e.g., a set of instructions comprising the program code of the control program) is located in the memory medium and transfer the control program instructions from the memory medium to the control program store rather than over the I2C bus. This can have a significant impact on the time used to update the control program and can allow for multiple versions of the control program to be available to the controller.

[0008] The terms "include," "have," and variations thereof, as used herein, mean the same as the term "comprise" or appropriate variation thereof. Furthermore, the term "based on," as used herein, means "based at least in part on." Thus, a feature that is described as based on some stimulus can be based only on the stimulus or a combination of stimuli including the stimulus.

[0009] Figures 1 is a block diagram depicting an example system 100 for updating a control program. Referring to Figure 1 , the example system 100 of Figure 1 generally includes a first storage medium 102, a second storage medium 104, and a controller engine 108 coupled to the first storage medium 102 and the second storage medium 104. The solid lines of Figure 1 that connect to the medium 102, medium 104, and/or controller engine 106 represent a physical connection (either direct or indirect) and the dotted lines of Figure 1 represent a logical connection, such as the transfer of data or reception of a signal. In general, the controller engine 106 can identify contents 103, such as a control program update instruction, in the second storage medium 104 and transfer the contents 103 to the first storage medium 102 dedicated to contain the control program of a controller.

[0010] The first storage medium 102 and the second storage medium 104 are each a non-transitory medium for storing data. In particular, the first storage medium 102 is dedicated to store program code of a control program and the second storage medium 104 is to store information routed by a system memory controller. In other words, the first storage medium 102 is managed to only contain a control program or the first storage medium 102 has a specific portion that is assigned to contain a control program. The control program is to contain instructions to enable operation of a controller over the second storage medium 104.

[0011] The controller engine 106 represents any circuitry or combination of circuitry and executable instructions to retrieve contents 103 from a location of the second non-transitory storage medium in response to a management control instruction 105 via a management bus and route the contents 103 (e.g., a control program image) to the first non-transitory storage medium. For example, the controller engine 106 can be the circuitry of a microcontroller where the microcontroller can include the first storage medium 102 in the circuitry or otherwise coupled to the microcontroller, where the control program to perform the operations of the microcontroller are located on the first storage medium 102. In that example, a common way to update the control program is through a communication interface, such as an I2C bus, but instead, the description herein describes a controller engine 106 that understands (e.g., recognizes and performs accordingly) a request by the communication interface to locate a control program update instruction from a different location, such as the second storage medium 104. The retrieve engine 107 represents a portion of the controller engine 106 to retrieve contents from the second non-transitory medium 104. The route engine 108 represents a portion of the controller engine 108 to route the contents from the second non-transitory storage medium 104 to the first non-transitory storage medium 102. [0012] An example context is where the microcontroller manages the second storage medium 104 where the second storage medium is accessible by a system memory controller for access by a processor resource of compute device. To update the control program, the control program update image (i.e., a set of instructions

representing an updated control program) is placed in the second storage medium 104 in a similar manner as to any data that may be stored in the second storage medium 104 by the system memory controller and a management controi instruction 105 is sent to the controller engine 108 where the management controi instruction 105 is to indicate to a controller that the control program is to be updated and indicate a location of an update to the program code (i.e., an instruction or set of instructions to replace existing program code) to route to the first storage medium 102.

[0013] The controller engine 108 can send a termination instruction to a system memory controller to terminate interactions with the second storage medium 104 in preparation for the controller engine 106 to take control over the second storage medium 104 and retrieve the control program image from the second storage medium 104. The controller engine 108 can identify the location of the control program image in the second storage medium 104 based on a parameter passed by the management control instruction 105. For example, a starting memory address may be provided with the management controi instruction 105 over the I2C bus. in this manner, the controller engine 106 can identify a first section of the second non-transitory storage medium 104 that contains a control program image and route data in a second section of the second non-transitory storage medium 104 to a third non-transitory storage medium (described in more detail with respect to Figures 2 and 3). For example, the controller engine 108 can route data of an NVDIMM from a DRAM storage medium to a first NV flash storage medium and the controi program image to a second NV flash storage medium (i.e., the control program store medium) in parallel. Examples of a flash storage medium include NV negative-and ("NAND") storage medium and a NV negative-or ("NOR") storage medium.

[0014] The second storage medium 104 can contain a plurality of versions of the control program. The controller engine 106 can select one of the plurality of control program versions based on the management control instruction 105, such as a parameter passed with the management control instruction 105. In this manner, the system 100 can maintain multiple control program versions and any one of the versions can be selected to execute. For example, the second storage medium 104 could be a NV flash storage medium (which provides for persistent storage) and the NV flash storage medium can contain a last known working version as well as the most-recently released version and if the most-recently released version contains an error, the control program of the last known working version can be loaded based on the management control instruction 105 from the I2C bus to flag the last known working version to be loaded at next boot.

[0015] The controller engine 108 has been described as circuitry or a

combination of circuitry and executable instructions and, as such, can be implemented in a number of fashions. For example, the controller engine 106 can comprise a memory resource capable of containing executable instructions and a processor resource for executing the executable instructions. The circuitry can be electronic circuitry, such as a combination of electrical elements (e.g., resistors, transistors, capacitors, inductors, diodes, and the like) to form the memory resource and the processor resource. Executable instructions can be processor-executable instructions, such as program code, that comprise any set of instructions to be executed directly (such as machine code) or indirectly (such as a script) by the processor resource and reside on the memory resource. The set of instructions can be operable, upon execution, to cause the processor resource to perform operations of the system 100. For example, the processor resource can carry out a set of instructions to, in response to management control instruction 105 requesting to update a first control program, identify a memory address of the second storage medium 104 having a second control program, copy the second control program from the second storage medium to the first storage medium to replace the first control program, and executing the system 100 to operate using the second control program. The controller engine 108 can be integrated info a compute device, such as a memory device, via circuitry or as installed instructions into a memory resource of the compute device, such as the first storage medium 102. For example, a controller (such as a microcontroller of an NVDIMM device) can comprise a controller engine 106. The controller engine 108 can be distributed across compute devices. In some example, the controller engine 108 can perform example methods described in connection with Figures 4-5.

[0016] A processor resource is any appropriate circuitry capable of processing (e.g., computing) instructions, such as one or multiple processing elements capable of retrieving instructions from the memory resource and executing those instructions. For example, the processor resource can be a central processing unit ("CPU") that enables updating a control program by fetching, decoding, and executing program code to transfer a control program to a particular location of a storage medium. Example processor resources include at least one CPU, a semiconductor-based microprocessor, a programmable logic device ("PLD"), and the like. Example PLDs include an

application specific integrated circuit ("ASIC"), a field-programmable gate array

("FPGA"), a programmable array logic ("PAL"), a complex programmable logic device ("CPLD"), and an erasable programmable logic device ("EPLD"). The processor resource can include multiple processing elements that are integrated in a single device or distributed across devices. The processor resource can process the instructions serially, concurrently, or in partial concurrence.

[0017] A memory resource represents any non-transitory medium or combination of non-transitory mediums able to electronically store data, such as program code or data used by the system 100. For example, the medium can be a storage medium, which is distinct from a transitory transmission medium, such as a signal. The medium can be machine-readable, such as computer-readable. The medium can be an electronic, magnetic, optical, or other physical storage device that is capable of containing (i.e., storing) executable instructions. A memory resource can be a nonvolatile memory resource such as read only memory ("ROM"), a volatile memory resource such as random access memory ("RAM"), or a combination thereof. Example forms of a memory resource include static RAM ("SRAM"), dynamic RAM ("DRAM"), electrically erasable programmable ROM ("EEPROM"), flash memory, or the like. A memory resource can include integrated memory such as a hard drive ("HD"), a solid state drive ("SSD"), or an optical drive. The memory resource can be integrated in the same device as the processor resource or it can be separate but accessible to that device and the processor resource. The memory resource can be distributed across devices.

[0018] Figure 2 is a block diagram depicting an example apparatus 200 that is able to update a control program. Referring to Figure 2, the example apparatus 200 can comprise a controller 208 (having circuitry 212 and a first storage medium 202), a second storage medium 204, and a third storage medium 210. The storage mediums 202, 204, and 210 each represent a non-transitory medium coupled directly or indirectly to the controller 208. In an example, the controller 208 can be on a chip with circuitry 212 and first storage medium 202 (where the first storage medium 212 is assigned to contain the control program for the controller 208) and the second storage medium 204 and the third storage medium 210 are located on the same substrate (e.g., the same printed circuit board ("PCB")), as the controller 208 coupled via connections of the substrate.

[0019] The apparatus 200 can represent a mixed memory device. For example, the first storage medium 202 can be a first flash storage medium (e.g., a flash memory device), the second storage medium 204 can be a volatile storage medium, and the third storage medium 210 can be a second flash storage medium.

[0020] The third storage medium 210 can store information from the second storage medium 204. For example with reference to Figure 3, the first storage medium can be NV NOR flash memory, the second storage medium can be DRAM, and the third storage medium can be NV NAND flash memory, where content of the DRAM is copied to the NV NAND flash memory in response to a system power event based on the controller.

[0021] The controller 206 can utilize circuitry 212 and/or first storage medium 202 to perform the functions of (and otherwise operate like) the controller engine 106 of Figure 1. For example, the circuitry 212 can be electrical circuitry to identify a memory address in one of the second storage medium 204 and the third storage medium 210 in response to receipt of a control instruction via a management bus (e.g., see I2C bus 326 of Figure 3), copy a first set of control program instructions from the location of the second storage medium 204, and initialize the controller 208 to be operable using the first set of control program instructions. The circuitry 212 can include an identify module 214, a copy module 218, and an initialize module 218, which represent circuitry or a combination of program instructions to enable the controller 206 to perform the operations discussed with regards to the controller engine 108 (e.g., identifying a location in the second storage medium 204 (or third storage medium 210) with a control program instruction, copying the control program instruction to the first storage medium 202, and causing the controller 206 to operate using the copied over control program instruction).

[0022] Figure 3 depicts an example system 320 in which various example apparatus 300 can be implemented. The example system 320 of Figure 3 comprises a system memory controller 322, a system processor 324, an 12C bus 326, a base board controller ("BMC") 328, and an example NVDIMM storage apparatus 300. The example NVDIMM storage apparatus 300 of Figure 3 comprises a volatile storage medium 304, a plurality of NV storage mediums 310, and a microcontroller 308. The microcontroller 308 of Figure 3 comprises circuitry 312 including a control program store 302

designated to store the control program of the microcontroller 306. The control program store 302 is a non-transitory storage medium. An example medium to use as the control program store 302 include flash memory, such as NV NOR flash memory, or any appropriate NV storage medium. The volatile storage medium and the NV storage medium can be an example non-transitory mediums discussed above with respect the description of Figure 1 regarding memory resources. For example, the volatile storage medium 304 can be a DRAM medium and a NV storage medium 310 can be a flash storage medium.

[0023] The system memory controller 322 is a controller over the memory used by a compute device for operation with a system processor 324 of the compute device. The system processor 324 can communicate with the NVDIMM storage apparatus 300 via an I2C bus 326 to the microcontroller 306. The system processor 324 can provide instructions or otherwise access the microcontroller 306. In particular, the system processor 324 can send a management control instruction via the I2C bus 326 to cause the microcontroller 308 to perform an update to the control program of the

microcontroller 306. Alternatively or in addition, a management control instruction can be sent to the microcontroller 308 by a BMC 328 coupled to the NVD! M storage apparatus 300 via the I2C bus 326.

[0024] The microcontroller 308 can also communicate with the system memory controller 322, the system processor 324, and the BMC 328, such as via the I2C bus 328, to facilitate modification to the control program. In an example of Figure 3, the microcontroller 308 can initiate a self-refresh mode on the microcontroller 308 in response to a management control instruction, verify a memory controller pipeline associated with the volatile storage medium 304 is empty based on communication with the system memory controller 322, cause control over the volatile storage medium 304 by the system memory controller 322 to be released, and reserve control over the volatile storage medium 304 for the microcontroller 308. In this manner, the

microcontroller 306 can ensure the data of the volatile storage medium 304 is not being manipulated at the time of copying the data to the control program store 302 and ensure the copying of the data is not interrupted.

[0025] In an example, the second storage medium (e.g., the volatile storage medium 304 of Figure 3) and/or the third storage medium (e.g., the NV storage medium 310 of Figure 3) can contain a plurality of sets of control program instructions. In other words, multiple versions of the control program can be located in one of the storage mediums 304 and 310 or distributed across storage mediums 304 and 310. For example, the multiple NV flash storage mediums 310 can exist where each NV flash storage medium 310 contains a different control program image (e.g., a different version of a microcontroller control program). In that example, a control instruction via the I2C bus 328 can indicate which version to load for the microcontroller 308 (such as by passing a parameter or using a particular function call of a plurality function calls to identify which location in memory contains the control program to load). The circuitry 312 can select one of the plurality of sets of control program instructions based on the control instruction (e.g., based on the parameter of the control instruction) and cause the controller 308 can load with the selected one of the plurality of sets of control program instructions (e.g., copy over the selected set of control program instructions and operate using those instructions). [0026] Figures 4 and 5 are flow diagrams depicting example methods for updating a control program of a microcontroller. Referring to Figure 4, example methods for updating a control program can generally comprise determining that a control instruction indicates that a first storage medium contains a control program image, identifying a section of the first storage medium that contains the control program image, and placing the control program image into a second storage medium on the microcontroller.

[0027] At block 402, an indication that a first storage medium contains a control program image is determined by a microcontroller based on a control instruction received via a management bus, such as an I2C bus.

[0028] At block 404, a section of the first storage medium contain the control program image is identified by the microcontroller using an advanced configuration and power interface ("ACPI") object. An ACPI object represents a data structure to contain data regarding the first storage medium, such as memory address information of the storage medium associated with the ACPI object. For example, the ACPI object can link to a memory map having the starting address of the control program image identified. The ACPI object can be relayed from the system memory controller managing the first storage medium or provided via the I2C bus.

[0029] At block 406, the control program image is placed into a second storage medium by the microcontroller. In reference to Figure 4, the second storage medium is a local control program store on the microcontroller. Once the control program image is loaded into the local control program store, the microcontroller can initialize and operate using the placed control program image.

[0030] Figure 5 includes blocks similar to blocks of Figure 4 and provides additional blocks and details. In particular, Figure 5 depicts additional blocks and details generally regarding preparing the DIMM on which the microcontroller resides for transferring the control program image, identifying DIMM information, selecting a control program image, and identifying the memory address of the control program image. Blocks 512, 518, and 518 are similar to blocks 402, 404, and 406 of Figure 4 and, for brevity, their respective descriptions are not repeated in their entirety. [0031] Ai block 502, the first storage medium is loaded with a control program via circuitry of the microcontroller. As mentioned herein, the first storage medium can be a volatile storage medium accessible by a system memory controller, which may perform the loading of the control program instruction onto the first storage medium. With the control program loaded in the first storage medium, the system is ready to update the microcontroller in-band via the first storage medium rather than over the relatively slower I2C bus. The control program image can be copied to persistent storage in a third storage medium. For example in the case of an environment where multiple control programs are to be loaded, a plurality of versions of microcontroller control programs can be copied from the DI M's DRAM to the DIMM's NV NAND flash storage medium for later retrieval.

[0032] At block 504, a memory map to locate the control program image is configured. For example, the memory map can be configured to associate a first memory address of a first section of the DIMM with the control program image and a second memory address of a second section of the DIMM with backup data. In this manner, the first section can be designated to transfer to the Iocal control program store and the second section can be designated to transfer to persistent NV memory on the DIMM, for example.

[0033] At block 506, an event that calls for a system backup is detected by the BMC and signaled to the microcontroller to initiate the data protection process to store data in persistent storage. Such an event can be any appropriate system power event, such as a thermal event, a graceful shutdown, and the like.

[0034] At block 508, iocal control over the first storage medium is given to the microcontroller. For example, control of the first storage medium is released from the system memory controller by setting a higher priority access to the microcontroller to allow for uninterrupted access to the first storage medium.

[0035] At block 510, DIMM information is identified. This can entail recognizing a DIMM is operational, retrieving DIMM information (e.g., retrieving an ACPI object and/or SPD information), and identifying at least one of a vendor of the DIMM and a

manufacture of the DIMM which may determine how to access the DIMM and may determine which version of the control program to select. [0036] Ai block 514, a control program image associated with the DIMM information retrieved at block 510 is selected. As discussed herein, the selection of the control program is based on the management control instruction received via the management bus. For example, the management control instruction can indicate which version of control program instructions is to be loaded and one of the plurality of versions of microcontroller control programs is selected to place in the local control program store based on the ACPI object of the DIMM and the context of the

management control instruction (e.g., the parameters of the management control instruction).

[0037] At block 518, the first section of the first storage medium containing the selected control program image is identified by parsing a starting memory address from the ACPI object. Using the size of the control program image, the contents of the memory address from the starting memory address to the end of the control program image can be transferred to the appropriate location in the local control program store on the microcontroller. By providing this capability in the microcontroller, the relatively low bandwidth communication channel of the I2C bus can be avoided by using a storage medium coupled to the microcontroller that is exposed to receiving data from the system memory controller.

[0038] Although the flow diagrams of Figures 4-5 illustrate specific orders of execution, the order of execution may differ from that which is illustrated. For example, the order of execution of the blocks may be scrambled relative to the order shown. Also, the blocks shown in succession may be executed concurrently or with partial

concurrence. Ail such variations are within the scope of the present description.

[0039] The present description has been shown and described with reference to the foregoing examples. It is understood, however, that other forms, details, and examples may be made without departing from the spirit and scope of the following claims. The use of the words "first," "second," or related terms in the claims are not used to limit the claim elements to an order or location, but are merely used to distinguish separate claim elements.