The contents of European patent application EP 16 161 038.1 is incorporated by reference.

The invention relates to a converter device for converting an input voltage into an output voltage according to the preamble of claim 1. Furthermore, the invention relates to a method to operate a converter device. In electronics devices point-of-load (PoL) DC-DC converters are needed to provide regulated DC voltages to various functional blocks in a system. Generally, these functional blocks require different voltage and power levels and, therefore, dedicated PoL converters are used for each block. For these systems, custom designs of the buck converter are used as the PoL converter of choice. The use of custom buck converters allows the designer to maximize efficiency and to minimize volume for each buck converter and to optimize the full system performance. However, custom buck converters increase the system-level design complexity and manufacturing costs and affect reliability. US 2008/0019158 Al discloses for example a conventional two-phase interleaved buck converter.

It is an object of the present invention to provide a highly flexible converter device that is able to provide a large range of voltages, conversion ratios and power levels with a high power processing efficiency, a low volume and a good dynamic performance.

This object is achieved by a converter device for converting an input voltage into an output voltage comprising the features of claim 1. The inventive converter device operates on the principle of transformability, which refers to its ability to choose its mode of operation based on operating conditions. This mode changing characteristic is enabled by seven switches, a flying capacitor and a controller. The controller is in particular a digital controller. The converter in particular comprises exactly seven switches to enable the different operation modes on the one hand and to avoid unnecessary losses on the other hand. Due to the seven switches and the flying capacitor the inventive converter device is in the following also called 7-switch flying capacitor converter device or 7SFC converter device. Correspondingly, the inventive converter is also called 7-switch flying ca- pacitor converter or 7SFC converter. Depending on the operating conditions, the converter device can operate in various operation modes, maximizing efficiency throughout the entire operating range. The operating conditions are characterized by at least one of the input voltage, the output voltage, a required output voltage, an output current, a required output current, a conversion ratio or a duty ratio. For example, at least two of the following operation modes can be provided: high step-down mode, 3-level buck mode, two-phase interleaved buck mode, single-phase 3-level buck mode and single-phase interleaved buck mode. The operation mode with the highest efficiency is selected by the mode selection logic. For example, the mode selection logic comprises a look-up table with predefined voltage thresholds and current thresholds. The converter device is at least one of a step-up converter device or a step-down converter device.

In case the converter device is operated as step-down converter device, there applies to a conversion ratio M = V _ou t/Vin: 1/24 < M < 1, preferably 1/48 < M < 1, preferably 1/80 < M < 1. Furthermore, in case the converter device is operated as step-up converter device, there applies to the conversion ratio M: 1 < M < 24, preferably 1 < M < 48, preferably 1 < M < 80. The converter device is operated at a switching frequency fs. For example, there applies to the switching frequency: 200 kHz < fs 1600 kHz, preferably 400 kHz < fs < 1400 kHz, preferably 600 kHz < fs < 1200 kHz.

Furthermore, there applies for example to a load current Load: 0,1 A < Load < 10 A, preferably 0,5 A < I _loa d < 8 A and preferably 1 A < I _loa d < 6 A.

A power processing efficiency of the converter device is defined as the ratio of the output power and the input power. The power processing efficiency depends on the conversion ratio M, the switching frequency fs and/or the load current Iioad. The power processing efficiency is at least 75 %, preferably at least 80 %, preferably at least 85 %, and preferably at least 90 % for the entire range of operating conditions. The converter device maintains a high and almost flat efficiency curve for the entire range of operating conditions.

A converter device according to claim 2 ensures a high degree of flexibility. The arrangement of the seven switches allows the inventive two-phase DC-DC converter to perform various different operation modes. Furthermore, the converter device enables a reduction of voltage stress across the reactive components to half of the input voltage in case of a step-down converter device or to half of the output voltage in case of a step-up converter device. The second input voltage terminal and the second output voltage terminal are in particular connected to the reference node. The reference node is in particular connected to ground. A converter device according to claim 3 ensures a high power processing efficiency due to a reduction in switching losses and voltage stress. The voltage across the flying capacitor is equal to half of the input voltage in case of a step-down converter device or half of the output voltage in case of a step-up converter device for certain operation modes. This enables a reduced voltage stress of the switches and the reactive components and a reduced volume of the reactive components. Furthermore, the switching losses of the switches are reduced.

A converter device according to claim 4 ensures a high degree of flexibility. Both inductors can be operated in parallel. This allows the load current to be split between the two inductors, reducing the volume requirement and losses of the inductors.

A converter device according to claim 5 ensures a high degree of flexibility. In case of a step-down converter device the output capacitor enables to adapt the output voltage ripple and the deviation of the output voltage to a desired value. The capacitor is in particular connected to the reference node.

A converter device according to claim 6 ensures a high degree of flexibility. The switch operation means provide switching signals to operate the switches dependent on the selected operation mode, namely the operation mode provided by the mode signal of the mode selection logic. The switch operation means comprise in particular a digital pulse width modulator.

A converter device according to claim 7 enables to provide a regulated output voltage. The voltage controller provides the switch operation means with a duty ratio to operate the switches dependent on said duty ratio. The output voltage is measured by a voltage sensor and preferably transferred into the digital domain by a corresponding analogue-to-digital converter. A digital voltage compensator is provided with an error signal which is the difference of a desired digital output voltage and the measured digital output voltage. The output signal of the digital voltage compensator is the duty ratio D. The duty ratio D is the ratio of a pulse duration T and a switching period Ts. There applies to the duty ratio: 0 < D < 1, in particular 0 < D < 1.

A converter device according to claim 8 ensures a high degree of flexibility and a high power processing efficiency. Based on signals, preferably digital signals of the input voltage, the output voltage and the output current the mode selection logic determines a suitable operation mode. For exam- pie, the mode selection logic uses a look-up table to provide a mode signal to the switch operation means which characterizes a suitable operation mode. In addition, the voltage compensator can be designed with different parameters, depending on the operation mode to achieve an optimized dynamic performance for each operation mode.

A converter device according to claim 9 ensures a high power processing efficiency for high step-down ratios under medium and heavy load conditions. This operation mode is called high step-down (HSD) mode. This mode provides the highest efficiency for high step-down cases. In steady- state, the voltage across the flying capacitor is equal to half of the input voltage of the converter. That means that all switches can be rated at half of the full input voltage. The benefits of a lower voltage rating for each switch are a reduced volume and reduced switching losses. A converter device according to claim 10 ensures a high power processing efficiency under light load conditions for cases when a high step-down conversion is required. This mode is called 3-level buck (3LB) mode. This mode is operated with both inductors in parallel by keeping the fifth switch and the seventh switch on over the full switching cycle. This allows the load current to be split between the two inductors, reducing the volume requirement and losses of the inductors. All switches are switched at half of the input voltage, reducing switching losses. A converter device according to claim 1 1 ensures a high degree of flexibility. This operation mode can be used for conversion ratios close to and greater than 0.5. This mode is called first two-phase interleaved buck (IBi) mode. This mode can be used for a duty ratio D > 0.5. A converter device according to claim 12 ensures a high degree of flexibility. This operation mode can be used for conversion ratios close to and greater than 0.5. This mode is called second two-phase interleaved buck (IB ₂ ) mode. This mode can be used for a duty ratio D < 0.5. A converter device according to claim 13 ensures a high degree of flexibility. This operation mode enables to perform phase shedding to further increase power processing efficiency at low currents. This operation mode is called single-phase 3-level buck (SP3LB) mode. A converter device according to claim 14 ensures a high degree of flexibility. This operation mode enables to perform phase shedding to further increase power processing efficiency at low currents. This operation mode is called single-phase interleaved buck (SPIB) mode. Furthermore, it is an object of the present invention to provide a highly flexible method to operate a converter device that is able to provide a large range of voltages, conversion ratios and power levels with a high power processing efficiency, a low volume, and a good dynamic performance.

This object is achieved by a method to operate a converter device comprising the steps of claim 15. The advantages of the method according to the invention correspond to the advantages already described of the converter device according to the invention.

Further features, advantages and details of the invention will be apparent from the following description of an embodiment which refers to the accompanying drawings. Fig. 1 shows a schematic diagram of a converter device with a converter and a digital controller, shows a first state of the converter in a high step-down mode, Fig. 3 shows a second and a fourth state of the converter in the high step-down mode, shows a third state of the converter in the high step-down mode, Fig. 5 shows a time diagram of voltages and currents of the converter in the high step-down mode,

Fig. 6 shows a first state of the converter in a 3-level buck mode, shows a second and a fourth state of the converter in the 3-level buck mode, shows a third state of the converter in the 3-level buck mode, shows a time diagram of voltages and currents of the converter in the 3-level buck mode, shows a first and a third state of the converter in a first two- phase interleaved buck mode, shows a second state of the converter in the first two-phase interleaved buck mode, shows a fourth state of the converter in the first two-phase interleaved buck mode, shows a time diagram of voltages and currents of the converter in the first two-phase interleaved buck mode, shows a first state of the converter in a second two-phase interleaved buck mode, shows a second state and a fourth state of the converter in the second two-phase interleaved buck mode, shows a third state of the converter in the second two-phase interleaved buck mode, shows a time diagram of voltages and currents of the converter in the second two-phase interleaved buck mode, shows a first state of the converter in a single-phase 3-level buck mode, shows a second state and a fourth state of the converter in the single-phase 3-level buck mode, shows a third state of the converter in the single-phase 3-level buck mode, shows a time diagram of a voltage and a current of the converter in the single-phase 3-level buck mode, shows a first state of the converter in a single-phase interleaved buck mode, shows a second state of the converter in the single-phase interleaved buck mode, shows a time diagram of a voltage and a current of the converter in the single-phase interleaved buck mode, shows efficiency curves of a conventional two-phase interleaved buck converter and the inventive converter for a first operating point, Fig. 26 shows efficiency curves of a conventional two-phase interleaved buck converter and the inventive converter for a second operating point and Fig. 27 shows efficiency curves of a conventional two-phase interleaved buck converter and the inventive converter for a third operating point.

Fig. 1 shows a converter device 1 for converting an input voltage VM into an output voltage Vout. The converter device 1 comprises a converter 2 and a digital controller 3 to operate the converter 2. The converter device 1 is for example used to convert the DC-DC input voltage VM into a smaller DC-DC output voltage Vout. A step-down ratio or a conversion ratio M is defined as follows: M = V _ou t/Vin.

The converter 2 comprises a first input voltage terminal ini and second input voltage terminal in ₂ to apply the input voltage VM. Furthermore, the converter 2 comprises a first output voltage terminal outi and a second output voltage terminal out ₂ to provide the output voltage Vout and an output current or load current Load to a load . The converter 2 further comprises for reactive components, namely a flying capacitor Cfi _y , a capacitor C, a first inductor Li and a second inductor L ₂ .

In case that the converter 2 is operated as step-down converter 2, the first input voltage terminal ini is connected via a first switch SWi to a first node Ni. The first node Ni is connected via the flying capacitor Cfi _y to a second node N ₂ . The second node N ₂ is connected via a second switch SW ₂ to a reference node No. The second node N ₂ further is connected via a third switch SW ₃ to a third node N3. The third node N3 is connected via the in- ductor Li with the first output voltage terminal outi. The first node Ni is further connected via a fourth switch SW ₄ to a fourth node N ₄ . Furthermore, the fourth node N ₄ is connected via a fifth switch SW ₅ to a fifth node N ₅ . The fifth node N ₅ is further connected via the second inductor L ₂ to the first output terminal outi. The fifth node N5 is connected via a sixth switch SW ₆ to the reference node No. The third node N3 is further connected via a seventh switch SW ₇ to the fourth node N ₄ . The output capacitor C is arranged in parallel to the first output voltage terminal outi and the second output voltage terminal out ₂ . This means that the first output voltage termi- nal outi is connected via the output capacitor C with the second output voltage terminal out ₂ . The reference node No, the second input voltage terminal in ₂ and the second output voltage terminal out ₂ are connected to ground. In case that the converter 2 is operated as step-up converter 2, the input voltage terminals ini, in ₂ and the output voltage terminals outi, out ₂ are exchanged. In this case the capacitor C is called input capacitor C.

The input voltage VM is measured by means of a first voltage sensor 4 and provided to an analog-to-digital converter 5. The analog-to-digital converter 5 transfers the input voltage VM into the digital domain and provides a digital input voltage signal V'm to the digital controller 3. Correspondingly, the output voltage V _ou t is measured by a second voltage sensor 6 and provided to a further analog-to-digital converter 7. The analog- to-digital con- verter 7 transfers the output voltage Vout into the digital domain and provides a digital output voltage signal VOut to the digital controller 3.

The digital controller 3 comprises a mode selection logic 8, switch operation means 9 and a digital voltage controller 10. The mode selection logic has three signal inputs to receive the input voltage V'k, a required output voltage Vref and a required output current I _re f. The mode selection logic 8 generates a mode signal S to select a suitable operation mode from a group of a different operation modes depending on the input voltage V'k, the re- quired output voltage V _re f and/or the required output current I _re f. For example, the mode selection logic 8 comprises a look-up table which generates the mode signal S dependent on the desired conversion ratio M and the load conditions which are characterized by the required output current I _re f. The switch operation means 9 are connected with the mode selection logic 8 to receive the mode signal S and to operate the switches SWi to SW ₇ dependent on the selected operation mode.

The digital voltage controller 10 comprises a voltage compensator 1 1 which receives an output voltage error signal e = V _re f - VOut. The voltage compensator 1 1 calculates a duty ratio D. The switch operation means 9 are connected to the digital voltage controller 10 to receive the duty ratio D and to operate the switches SWi to SW ₇ dependent on the duty ratio D. The duty ratio D is the ratio between a desired pulse duration and a switching period Ts.

The switch operation means 9 are connected to the switches SWi to SW ₇ and generate for each switch SWi to SW ₇ a corresponding switching signal Gi to G ₇ . The switches SWi to SW ₇ are switched on or switched off depending on the signal level of the corresponding switching signal Gi to G ₇ . The switches SWi to SW ₇ are for example MOSFETs.

The switch operation means 9 comprise a first switching sequence to perform a first operation mode. This operation mode is called high step-down mode or HSD mode. The switching sequence of the HSD mode is as follows:

wherein SWi to SW ₇ denote the mentioned seven switches and STi to ST ₄ denote four states of a switching cycle. Furthermore, 0 means OFF and 1 means ON.

Fig. 2 to fig. 4 show the converter 2 in the states 1 (STi) to 4 (ST ₄ ) of the switching cycle. Furthermore, fig. 5 shows a time diagram of the voltages VLI and VL2 across the inductors Li and L ₂ and of the currents iu and iL2 through the inductors Li and L ₂ . t denotes the time and Ts the switching period of the switching cycle. The duration of the states 1 to 4 depends on the duty ratio D.

The HSD mode has a high power processing efficiency for high step-down ratios M under medium and heavy load conditions. In steady-state, the voltage Vcfiy across the flying capacitor Cfi _y is equal to half of the input voltage Vin. The switching sequence consists of the four states STi to ST ₄ , where in state 1 the flying capacitor Cfi _y and the inductor Li are charged with energy. State 2 is a synchronous rectification state. In this state 2 the inductor currents iu and iL2 are divided. Due to this current distribution the power losses are reduced. During state 3 the flying capacitor Cfi _y is discharged and the inductor L ₂ is charged. State 4 is a repetition of state 2.

The flying capacitor voltage Vcfiy is maintained at Vk/2 by the two inductors Li and L ₂ and the conversion ratio is M (D) = V _ou t/Vin = D/2. In the HSD mode the variations of the switching node voltages VLI and VL2 are reduced by a half compared to a conventional two-phase interleaved buck converter, allowing for a significant reduction of the inductance value of the inductors Li and L ₂ . Since the capacitors Cay and C have up to three orders of magnitude smaller volume for the same amount of stored energy than the inductors Li and L ₂ the overall volume of reactive components of the converter 2 is reduced compared to a conventional two-phase interleav- ed buck converter. In the HSD mode all switches S Wi to S W ₇ are blocking only a half of the input voltage VM. This means that, if the same silicon area is used for the two implementations, both switching and conduction losses for semiconductor components of this topology could potentially be smaller than that of a conventional two-phase interleaved buck converter.

The switch operation means 9 further comprise a second switching sequence to perform a second operation mode. This second operation mode is called 3-level buck mode or 3LB mode. The switching sequence of the 3LB mode is as follows: wherein SWi to SW ₇ denote the mentioned seven switches and STi to ST ₄ denote four states of a switching cycle. Furthermore, 0 means OFF and 1 means ON.

Fig. 6 to 8 show states 1 (STi) to 4 (ST ₄ ) of the converter 2 in the 3LB mode. Furthermore, fig. 9 shows a time diagram of the voltages VLI and VL2 across the inductors Li and L ₂ and of the currents iu and iL2 through the inductors Li and L ₂ .

In state 1 the flying capacitor Cfi _y is charged through the inductors Li and L ₂ . State 2 is a synchronous rectification state. In state 2 the inductor currents iu and iL2 are divided. In State 3 the flying capacitor Cfi _y is dis- charged to maintain approximately a constant Vk/2 voltage level of Vcfiy. State 4 is a repetition of state 2.

The 3LB mode can be used under light load conditions, for cases when a high step-down conversion ratio M is required, for example M < 0.5. In the 3LB mode switches SW ₅ and SW ₇ are turned on all the times and the in- ductors Li and L ₂ are in parallel. This allows the output current Load to be split between the two inductors Li and L ₂ , reducing the volume requirement and the losses of the inductors Li and L ₂ . The 3LB mode operates with a range of the duty ratio D of 0 < D < 0.5 and a conversion ratio of M (D) = D. The switches SWi to SW ₇ are switched at half of the input voltage Vin, reducing the switching losses.

The switch operation means 9 further comprise a third switching sequence to perform a third operation mode. This operation mode is called first two- phase interleaved buck mode or IBi mode. The switching sequence of IBi mode is as follows:

wherein SWi to SW ₇ denote the mentioned seven switches and STi to ST ₄ denote four states of the switching cycle. Furthermore, 0 means OFF and 1 means ON. The IBi mode can mainly be used for conversion ratios M close to or greater than 0.5. The conversion ratio M for the IBi mode is M (D) = D, wherein for the duty ratio D applies: D > 0.5. Fig. 10 to fig. 12 show state 1 (STi) to state 4 (ST ₄ ) of the converter 2 in the IBi mode. Furthermore, fig. 13 shows a time diagram of the voltages VLI and VL2 across the inductors Li and L ₂ and the currents iu and iL2 through the inductors Li and L ₂ .

In state 1 both inductors Li and L ₂ are charged with the input voltage VM at the nodes N ₃ and N ₅ . In state 2 the inductor Li continues charging while the inductor L ₂ is in synchronous rectification. State 3 is a repetition of state 1 . In state 4 the inductor L ₂ continues charging while the inductor Li is in synchronous rectification. To keep all of the switch ratings at Vi _n , max/2 this operation mode is used for VM < V _M , max/2, where V _M , max is the highest allowable input voltage for the converter 2. Since the switches SWi, SW ₂ and SW ₄ remain on in states 1 to 4 the capacitor voltage Vcfiy is held at the input voltage VM.

The switch operation means 9 further comprise a fourth switching sequence to perform a fourth operation mode. This operation mode is called second two-phase interleaved buck mode or IB ₂ mode. The switching sequence of the IB ₂ mode is as follows:

wherein SWi to SW ₇ denote the mentioned seven switches and STi to ST ₄ denote four states of a switching cycle. Furthermore, 0 means OFF and 1 means ON. In general the IB2 mode corresponds to the IBi mode, whereas for the duty ratio D applies: D < 0.5.

Fig. 14 to fig. 16 show state 1 (STi) to state 4 (ST ₄ ) of the converter 2 in the IB ₂ mode. Furthermore, fig. 17 shows the voltages VLI and VL2 across the inductors Li and L2 and the currents iu and iL2 through the inductors Li and L2. In state 2 and state 4 both inductors Li and L2 are discharged. For further details it is referred to the description of the IBi mode.

The switch operation means 9 further comprise a fifth switching sequence to perform a fifth operation mode. This operation mode is called single- phase 3-level buck mode or SP3LB mode. The switching sequence of the SP3LB mode is as follows:

wherein SWi to SW ₇ denote the mentioned seven switches and STi to ST ₄ denote four states of the switching cycle. Furthermore, 0 means OFF and 1 means ON. Fig. 18 to fig. 20 show state 1 (STi) to state 4 (ST ₄ ) of the converter 2 in the SP3LB mode. Furthermore, fig. 21 shows the voltage VLI across the inductor Li and the current iu through the inductor Li. In general the SP3LB mode corresponds to the 3LB mode, however, the SP3LB mode uses phase shedding to further increase power processing efficiency at low currents. For further details it is referred to the description of the 3LB mode.

The switch operation means 9 further comprise a sixth switching sequence to perform a sixth operation mode. This operation mode is called single- phase interleaved buck mode or SPIB mode. The switching sequence of the SPIB mode is as follows:

wherein SWi to SW ₇ denote the mentioned seven switches and STi and ST ₂ denote two states of the switching cycle. Furthermore, 0 means OFF and 1 means ON. Fig. 22 and fig. 23 show state 1 (STi) and state 2 (ST2) of the converter 2 in the SPIB mode. Furthermore, fig. 24 shows the voltage VLI across the inductor Li and the current iu through the inductor Li. In general the SPIB mode corresponds to state 1 and state 4 of the IBi mode, however, the SPIB mode uses phase shedding to further increase power processing effi- ciency at low currents. For further details it is referred to the description of the IBi mode.

The mode selection logic 8 determines depending on the input voltage V'k, the required output voltage V _re f and the required output current I _re f a suita- ble operation mode. This suitable operation mode is selected from the operation modes mentioned before. For example, the mode selection logic 8 determines a suitable operation mode using a look-up table with predefined voltage thresholds and current thresholds such that the look-up table stores which modes have the highest efficiency for specific operating conditions. The mode selection logic 8 sends a corresponding mode signal S to the switch operation means 9 which contain the mentioned switching sequences for each operation mode. Using the duty ratio D from the voltage compensator 1 1 and the mode signal S from the mode selection logic 8, the switch operation means 9 operate the switches SWi to SW ₇ accordingly. In addition, the voltage compensator 1 1 can be designed with different parameters depending on the operation mode, to achieve an optimized dynamic performance for each mode. The converter device 1 is compared to a conventional two-phase interleaved buck converter as known from US 2008/00191 58 Al . The switching frequency used for comparison is 800 kHz. To compare the volume of the reactive components of the converter 2 to a conventional two-phase interleaved buck converter the energy storage requirements are compared. To achieve the same current ripple in the inductors, the inductance of the converter 2 can be reduced about 33 %, resulting in smaller inductors Li and L ₂ . Furthermore, to achieve a desired output voltage deviation in response to a load transient, the required output capacitor C for the converter 2 can be about 33 % smaller than the conventional two-phase interleaved buck converter to achieve the same transient performance. To show the efficiency improvements of the converter device 1 over the conventional two-phase interleaved buck converter, the following three operation points are compared between the mentioned converters:

Operation point 1 : VM = 12V and V _ou t = IV,

Operation point 2: VM = 12V and V _ou t = 5V,

Operation point 3 : VM = 36V and V _ou t = 12V. Fig. 25 shows efficiency curves for the conventional two-phase interleaved buck converter (left side) and the converter 2 operating in the HSD mode (right side) for operation point 1. The purpose of the HSD mode is to achieve highest efficiency for high step-down ratios. At operation point 1 the HSD mode improves on the efficiency of the conventional two-phase interleaved buck converter for the entire range of load currents Load. The HSD mode enables a loss reduction in the switching losses resulting in the improved efficiency. Fig. 26 shows efficiency curves for the conventional two-phase interleaved buck converter (left side) and the 3LB mode and the IBi mode of the converter 2 (right side) for operation point 2. For operation point 2 the highest efficiency mode of the converter 2 depends on load currents I ad. At the low end of load currents, the 3LB mode has significantly higher efficiency compared to the conventional two-phase interleaved buck converter and compared to the IBi mode. As the load current is increased the IBi mode becomes the highest efficiency mode. For this segment of load currents the converter 2 achieves almost equivalent efficiency compared to the conventional two-phase interleaved buck converter. The slightly reduced efficien- cy is caused by higher conduction losses of the IBi mode compared to the conventional two-phase interleaved buck converter.

Fig. 27 shows efficiency curves for the conventional two-phase interleaved buck converter and the 3LB mode of the converter 2 for operation point 3. The 3LB mode of the converter 2 has an improved efficiency at light and medium loads for high input voltages. This results from a reduced switch blocking voltage and voltage swing.

By properly selecting operation modes of the converter 2, efficiency im- provements are achievable over the full operating range.

The converter device 1 provides a high power density wide-input DC-DC highly flexible converter topology for a wide range of point of load applications. The converter 2 is called 7-switch flying capacitor converter or 7SFC converter. The converter 2 requires much smaller inductors Li and L ₂ compared to a conventional two-phase interleaved buck converter and, at the same time, improves power processing efficiency. These advantages are achieved by reducing the voltage swing across the inductors Li and L ₂ and the voltage stress of all switches SWi to SW ₇ to a half of the full input voltage for several operation modes. The converter device 1 has in summary the following advantages: multi-mode switch operation, in particular facilitated by the digital controller 3,

operating point based efficiency optimization,

significantly improved high step-down ratio efficiency over a conventional two-phase interleaved buck converter by significantly reducing switching losses,

- reduced inductor volume requirement,

reduced output capacitor requirement,

a reduced silicon area for the switches SWi to SW ₇ compared to a conventional two-phase interleaved buck converter.