Title:
A/D CONVERTER
Document Type and Number:
WIPO Patent Application WO/2019/087809
Kind Code:
A1
Abstract:
According to the present invention, the power consumption of an A/D converter including an adder, a quantizer, a prediction filter, and a decimation filter is reduced. An A/D converter 1A is provided with an adder 2, a quantizer 3, a prediction filter 4, a decimation filter 5, and a compensation filter 6. The adder 2 calculates the difference between an analog input signal U and a prediction value P. The quantizer 3 quantizes the above difference and converts the analog input signal U into a digital data string of a word length WL0. The prediction filter 4 generates the prediction value P of a word length WL1 from the above digital data string. The decimation filter 5 attenuates high frequency noise from an output of the quantizer 3, lowers a data frequency from fs to fo, and converts the output of the quantizer 3into multi-bit data at a low speed of a word length WL2. The compensation filter 6 compensates for frequency characteristics of output data and outputs data of the word length WL0 with the data frequency fo.
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Inventors:
TAKASE YASUHIDE (JP)
Application Number:
PCT/JP2018/038902
Publication Date:
May 09, 2019
Filing Date:
October 18, 2018
Export Citation:
Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H03M3/02; H04B14/04
Domestic Patent References:
| WO2016021382A1 | 2016-02-11 | |||
| WO2017179508A1 | 2017-10-19 |
Foreign References:
| JP2013042488A | 2013-02-28 | |||
| JPH10509544A | 1998-09-14 |
Other References:
FELTON, CHRISTOPHER L. ET AL.: "A Comparison of Efficient First Stage Decimation Filters for Continuous Time Delta Sigma Modulators", 2017 51ST ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS, AND COMPUTERS, 29 October 2017 (2017-10-29), pages 473 - 477, XP033346082, DOI: doi:10.1109/ACSSC.2017.8335384
Attorney, Agent or Firm:
MINEGISHI Takeshi (JP)
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