CROSS-REFERENCE TO RELATED APPLICATION

[0001] This patent document claims priority to and benefits of U.S. Provisional Patent Application No. 62/856,646 entitled“CONVOLUTIONAL PRECODING AND DECODING OF POLAR CODES” and filed on June 3, 2019. The entire content of this patent application is incorporated by reference as part of the disclosure of this patent document.

TECHNICAL FIELD

[0002] This document generally relates to error correction codes, and more particularly to convolutional precoding and decoding of polar codes.

BACKGROUND

[0003] A communications system generally adopts channel encoding to improve reliability of data transmission and ensure quality of communications in the presence of various types of noise and errors. Polar coding is a general and extremely powerful error-correction technology proposed around a decade ago, and which is currently used for coding the control channels in the eMBB mode of the Fifth Generation (5G) wireless standard. In addition to wireless

communications, polar codes may have applications in fiber-optic networks, data storage, satellite communications, and more.

SUMMARY

[0004] Embodiments of the disclosed technology relate to methods, systems and devices for the convolutional precoding and decoding of polar codes that can be used in various

communication systems, including but not limited to wireless systems, wired systems, and data storage systems. The described embodiments advantageously enable the exchange of voice, video, data, and other information with lower implementation complexity and better error correction capabilities, thereby supporting high-date rates in high-mobility environments.

[0005] In an example aspect, a method for improving an error correction capability of a decoder includes receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis, and performing, based on the trellis, a list-decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages, wherein an z-th symbol of any noisy codeword of the outer stream decodable code could be decoded to a valid symbol based on a first i+w symbols of the noisy codeword, wherein each codeword of the outer stream decodable code has a length of n symbols, with n > i +w, and wherein //, z, and w are positive integers.

[0006] In another example aspect, a method for improving an error correction capability of an encoder includes receiving a plurality of information symbols, generating a plurality of convolutionally encoded symbols by performing a convolutional encoding operation on the plurality of information symbols, wherein the convolutional encoding operation is based on a time-varying trellis, generating a plurality of polar encoded symbols by performing a polar encoding operation on the plurality of convolutionally encoded symbols, and providing the plurality of polar encoded symbols for transmission or storage.

[0007] In yet another example aspect, the above-described methods may be implemented by an apparatus or device that comprises a processor and/or memory.

[0008] In yet another example aspect, these methods may be embodied in the form of processor-executable instructions and stored on a computer-readable program medium.

[0009] The subject matter described in this patent document can be implemented in specific ways that provide one or more of the following features.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 illustrates an example of the convolutional pre-coding of polar codes.

[0011] FIG. 2 illustrates an example of an algorithm that generates a puncturing pattern.

[0012] FIG. 3 illustrates an example of a convolutional list successive cancellation decoder.

[0013] FIG. 4 compares the frame error rate (FER) performance of cyclic redundancy check

(CRC)-aided list successive cancellation (LSC) decoding and convolutional LSC decoding.

[0014] FIG. 5 is a flowchart of an example method for convolutional LSC encoding.

[0015] FIG. 6 is a flowchart of an example method for convolutional LSC decoding.

[0016] FIG. 7 is a block diagram representation of a portion of an apparatus, in accordance with some embodiments of the presently disclosed technology.

DETAILED DESCRIPTION

[0017] Polar codes are a new approach to maximizing the rate and reliability of data transmissions. In an example, polar codes have been adopted to improve coding performance for control channels in 5G. At the same time, they reduce the complexity of design and ensure service quality. Polar codes are a type of linear block error correcting code, whose code construction is based on a multiple recursive concatenation of a short kernel code which transforms the physical channel into virtual outer channels. When the number of recursive concatenations becomes large, the virtual channels tend to either have very high reliability or very low reliability (in other words, they polarize), and the data bits are allocated to the most reliable channels.

[0018] Embodiments of the disclosed technology relate to convolutional precoding and decoding of polar codes that among other features and benefits reduce a communication receiver’s complexity while realizing the potential of the performance of polar codes. The disclosed embodiments can, for example, be used to reduce the required list size in list successive cancellation (LSC) (or successive-cancellation list (SCL)) decoding of polar codes, which in turn reduces the overall computational complexity of the decoder. Simulation results indicate that a reduction of at least 50 percent in list sizes can be achieved. In example embodiments, the precoding is designed based on a time-varying puncturing pattern of convolutional codes that provides a balanced error correction over unfrozen polarized bit- channels, which are also known as unfrozen synthesized channels.

[0019] Section headings are used in the present document to improve readability of the description and do not in any way limit the discussion or embodiments (and/or implementations) to the respective sections only. Accordingly, embodiments disclosed in different sections can be used with each other.

[0020] Introduction to polar codes and list successive cancellation list (LSC) decoding

[0021] Polar codes. In the present document, embodiments of the disclosed technology use a (n, k) polar encoder, where n = 2 ^m corresponds to m levels of polarization and k denotes the number of information bits in the polar code, resulting in n— k frozen bits. In some

embodiments, the frozen bits are set to zero. In other embodiments, the frozen bits are computed dynamically. In yet other embodiments, the frozen bits are computed such that they are known a priori at both the transmitter and the receiver. The relationship between the transmitted symbols (x and the uncoded information bits (li is given by: x - u G _rn , G _rn _ - B o _n r [i ₁ of ^m

[0022] Herein, x = u G _n is referred to as a polar transformation, and G _n is the polar code generator (or generating) matrix. In some embodiments, the polar code generator matrix is the m- th Kronecker power of the 2x2 kernel matrix that is multiplied by a length-^ bit reversal matrix B _n and u denotes the uncoded information bit vector that includes k information bits and n— k frozen bits. In an example, the 2x2 kernel matrix (denoted F) and the m- th Kronecker power of the kernel matrix for m = 3 are given by:

rl 0 0 0 0 0 0 0i

1 1 0 0 0 0 0 0

1 0 1 0 0 0 0 0

1 1 0 0 1 1 0 0

1 0 1 0 1 0 1 0

L1 1 1 1 1 1 1 1 ^J

[0023] In some embodiments, different 2x2 kernel matrices (e.g., Jj) may be used to

generate the polar code. In other embodiments, a N*N kernel matrix may be used to generate the polar code, where N > 2. In yet other embodiments, the bit reversal matrix B _n may be omitted in the generation of the polar code.

[0024] List successive cancellation decodins. List successive cancellation (LSC) decoding of polar codes is typically performed during decoding at the receiver, and operates by generating L codeword candidates where L is called the list size. The value of L determines the trade-off between error-correcting performance and the computational complexity.

[0025] When list successive cancellation decoding is performed, at each stage of the decoding process, the list of L survivor candidates is maintained. For example, during list successive cancellation decoding, at each stage, the previous decoded values are used to decode the current value. During decoding, if a bit value is not known, an LSC decoder first assumes that the value is“0” and then“1,” and performs the decoding operation for both cases. The number of assumptions that can be made during the decoding process corresponds to the list size L. It has been shown that LSC decoding approaches maximum likelihood (ML) decoding for moderate list sizes. In some existing implementations, and to match the performance of Turbo and LDPC codes, for example, a cyclic redundancy check (CRC) code is serially concatenated with the polar codes and the CRC bits are used to choose the valid codeword from the candidates of the LSC decoder, albeit at the expense of greater complexity. CRC checkpoints provide some auxiliary information that can help the decoder detect a few mistakes it may have made throughout the decoding process.

[0026] Overview of convolutional precoding and decoding of polar codes

[0027] Embodiments of the disclosed technology replace the CRC with a convolutional code to advantageously provide a continuous and purposefully-unequal layer of protection to all of the information rather than one or a few checkpoints. In contrast to the CRC that is only capable of validating an entire or a large segment of the information vector, which gives little to no information about the location of the decoding mistake and forces the decoder to guess the location based on statistical knowledge, a convolutional code provides an exact location for the mismatched symbol. The use of convolutional codes does not necessarily increase the minimum distance, but provides a local error correction capability on the go. In this document, an error correction code that provides this on-the-go local error correction capability (including, but not limited to, the convolutional code described herein) is referred to as a“stream decodable code.”

[0028] The convolutional code works as an additional layer of protection over polar information bits. Since many of the information bits associated with polar bit-channels that are essentially noise-free and hence do not require further protection, which is a result of channel polarization, embodiments of the disclosed technology provide puncturing patterns over the systematic convolutional code to avoid over-protection, thereby increasing the overall code rate.

[0029] Furthermore, convolutional precoding and decoding of polar codes advantageously enables reaching the desired decoding error probability with smaller list sizes in the successive cancellation decoding algorithm of polar codes, which translates to lower computational complexity for the decoder. Lower computational complexity translates to smaller chip size, higher throughput, and less power consumption in wireless communication.

[0030] Examples of encoding structures for embodiments of the disclosed technology

[0031] FIG. 1 illustrates an example of a concatenation scheme between an ( n , k) polar code (120) and a high-rate (k, £) convolutional code (110), with the overall rate being given by £ //. In some embodiments, the high-rate convolutional code is be generated in at least two ways:

[0032] (1) a higher-complexity convolutional code with large number of states that has a large mother code-rate; or

[0033] (2) a lower-complexity convolutional code with a moderate number of states and a time-varying puncturing pattern.

[0034] According to embodiments of the disclosed technology, the convolutional code provides a local error correction capability on the go, and is configured to have a small decoding delay. The decoding delay in convolutional codes is linked to their traceback depth parameter, which is itself linked with the constraint length of the code. In an example, the traceback depth of a convolutional code with mother code-rate 1/2 can be estimated as five times its constraint length. In another example, the traceback depth may be greater for heavily punctured

convolutional codes.

[0035] In an example, the generator matrix of a rate- 1/2 mother convolutional code is denoted G _conv = [1 + D ² , 1 + D + D ² ] . The encoder prior to the puncturing can be described as:

[0036] Herein, i = 1, 2, = 0. Hence, the additional encoding complexity is linear in block-length which does not increase the overall asymptotic complexity of

0(n log n). In this framework, the structure of the convolutional polar decoder does require termination of the convolutional code. Thus, the mother convolutional code can be viewed as a (2£, £) linear block code, where the value of £ is determined according to the extra redundancy associated with the convolutional precoding, r = £ k.

[0037] The high-rate convolutional code illustrated in FIG. 1 can be generated by puncturing some 2 £ k coordinates on the mother code. If it is assumed that the z-th convolutional symbol is denoted (u _2i-1 , u _2i ), then it is intuitively clear that a convolutional code whose z-th symbol is not punctured at all provides a better local correction around the z-th symbol than the same convolutional code with one or both bits in its z-th symbol punctured. Based on this approach, the disclosed puncturing algorithm punctures a bit in all but £ k symbols where the non-punctured symbols appear around more noisy bit-channels.

[0038] An example of a puncturing algorithm

[0039] According to some embodiments of the disclosed technology, a method to design a time-varying puncturing pattern for convolutional codes is beneficial in scenarios where the underlying transmission channel is time-varying or unequal error protection is desired. For example, the non-periodic puncturing pattern for convolutional codes that is designed can be used to balance out the bit error probabilities of a time-varying underlying communication channel. This is based on partitioning different instances of the communication channel into subgroups with almost equal accumulated errors in each and then assigning an equal number of redundancy bits to each subset.

[0040] In some embodiments, the bit-channels can be partitioned into r subsets S _L for i =

1, ... r while preserving their order, which results in all bit-channels in set i appearing before the bit-channels in set j during the SC decoding for all i < j. Furthermore, the noise is balanced such that the probability of making a mistake in each group is roughly the same. These probabilities can be formulated by

[0041] The algorithm starts with an empty subset, and bit-channels are added one by one to the subset while assigning a punctured symbol to each until the overall error probability of the bit-channels inside the subset reaches the rough threshold of

[0042] When this threshold is reached, a non-punctured symbol is assigned instead. The algorithm then proceeds to the next partition similarly. Thus, each partition ends up with exactly one non-punctured symbol, which is the additional parity that is there to provide a local error correction throughout the SC decoding. In other embodiments, more than one additional parity is assigned to each partition.

[0043] FIG. 2 illustrates an example implementation for generating the puncturing pattern, wherein the noise levels are given by q _j =— log(l— p _; ). As illustrated therein, the output of the algorithm is a binary vector c of length 2£ that corresponds to the puncturing pattern on the length 2£ convolutional code, where q = 1 when the z-th bit is punctured. In this example, numerical simulations suggest puncturing the first bit rather than the second one in the convolutional symbols (see line 9 in FIG. 2). [0044] In some embodiments, the time-varying puncturing patterns can be used to improve the performance of a hybrid ARQ (automatic repeat request) scheme that uses incremental redundancy (IR) in a time-varying transmission channel. Upon determining that a transmission has not been successfully decoded at the receiver, an IR-HARQ scheme typically transmits different sets (and/or an increasing number) of parity bits in subsequent re-transmissions to improve the received SNR. Different redundancy versions of the output of the encoder (of a low- rate mother code) may be generated using the time-varying puncturing patterns.

[0045] In some embodiments, the time-varying puncturing patterns may be used to improve the performance of rate-adaptive coding and modulation schemes. In this framework, the channel is periodically evaluated at a receiver and an estimate (prediction) of the future channel state is sent back to a transmitter on a separate channel. Thus, the transmitter adapts to the instantaneous channel quality by choosing between different available transmission schemes of varying spectral efficiencies, which may be designed using the time-varying puncturing patterns as described in this document.

[0046] In some embodiments, the time-varying puncturing patterns may be used to provide unequal error protection (UEP), which is frequently used in integrated voice and data

transmission over band-limited channels. For example, recent source coding techniques (e.g., code-excited linear prediction) can provide good quality speech but some of the source coder output bits are more sensitive to transmission errors than others. The time-varying puncturing patterns described in this document are well suited for this application. UEP exploits the fact that less noisy bit-channels require less secondary protection. Thus, equalizing the error levels of the unfrozen polar bit-channels improves the frame error rate (FER) significantly.

[0047] Example of decoding structures for embodiments of the disclosed technology

[0048] According to embodiments of the disclosed technology, the convolutional code (e.g.,

110 in FIG. 1) is not used just to verify the output of the successive cancellation decoder (as is the case when using the concatenated CRC code). Instead, the convolutional code is used to modify the decoding algorithms to only follow those paths that correspond to the valid convolutional codewords. Therefore, there are no checkpoints in this algorithm and the secondary error detection mechanisms are replaced with an error prevention scheme. Moreover, the performance enhancement is provided in a more balanced way among the bit-channels than the checkpoints in the CRC-aided scheme. [0049] Thus, the proposed decoding algorithms, during the list successive cancellation decoding, keep track of the valid codewords over the trellis that corresponds to the underlying convolutional code. By doing so, the decoder only explores codewords that are validated on the go and hence prevents unnecessary calculations.

[0050] In an example, assume a (16, 8) polar code has unfrozen indices {ί ₁ ... , t ₈ }, and which has been precoded with a (12, 6) convolutional code that is punctured at indices ( 1, 3, 7, 9}. The convolutional SC decoder reveals polar non-frozen bits in the following ordered batches:

[0051] Although it is possible to implement a convolutional SC decoder, one of the main advantages, amongst others, of precoding with a convolutional code appears in the convolutional LSC decoder. There are typically two general methods to implement a list decoder that tracks paths on the trellis of the convolutional code, which differ only in their pruning methods.

Assume the list size is given by L. The first implementation of the convolutional LSC decoder performs sequential decoding over the trellis while tracking the L most likely paths ending at the same symbol slot. At each step, it generates 2 L new paths, of which L most likely ones are selected for the decoding step that follows.

[0052] In the second method, the list size L is fixed and equal to the maximum number of states in the encoder. This is typically given by 2 ^V , where v is the number of memory elements. Here, the decoder tracks the L more likely paths, where each path ends in a different state. In each iteration of the decoder, 2 L new paths are generated, which give two different options to choose from for the paths ending in each state, and wherein the less likely one is discarded. This resembles the Viterbi Algorithm of convolutional codes as depicted in the example in FIG. 3. As illustrated therein, for symbol s _i+1 , each of the 4 paths ends in a different state, and 8 new paths are computed using the convolutional LSC decoder. For each state in symbol s _i+1 , the more likely path among the two options is kept and the other one is discarded.

[0053] Numerical simulations suggest that the second method is more efficient in some embodiments, since keeping track of decoding path endings in different states provides a form of diversity that helps with the recovery of the correct path if it diverges from the ML path through decoding. FIG. 4 compares the frame error rate (FER) performance of CRC-aided LSC decoding and convolutional LSC decoding. In this example, the polar code is has length «=512 and rate 1/2, the last 8 information bits are used for the CRC (in the CRC-aided LSC decoding) and 8 non-punctured symbols are selected based on the puncturing algorithm described earlier (in the convolutional LSC decoding). As illustrated therein, convolutional LSC decoding outperforms CRC-aided LSC decoding with the same L (e.g., L=4 in FIG. 4), and is marginally worse than CRC-aided LSC decoding with double the list size (e.g., L=8 in FIG. 4).

[0054] Computational complexity

[0055] The computational complexity of tracking the codewords over the trellis is linear in block-length. The computational complexity of the convolutional LSC decoder is dictated by the list size or equivalently by the number of states in the convolutional encoder, which can be represented as 0(2 ^v n logn). In an example wherein a strong convolutional code may be used, a larger number of states may be present, which necessitates either increasing the list size or using a sub-optimal decoder.

[0056] Methods and implementations of the disclosed technology

[0057] FIG. 5 is a flowchart for improving an error correction capability of a encoder. The method 500 includes, at operation 510, receiving a plurality of information symbols.

[0058] The method 500 includes, at operation 520, generating a plurality of convolutionally encoded symbols by performing a convolutional encoding operation on the plurality of information symbols (e.g., block 110 in FIG. 1), wherein the convolutional encoding operation is based on a time-varying trellis. In some embodiments, the time-varying trellis includes a different number of outgoing branches from each state at different times. In other embodiments, the time-varying trellis includes a different number of states at each decoding stage and/or time.

[0059] The method 500 includes, at operation 530, generating a plurality of polar encoded symbols by performing a polar encoding operation (e.g., block 120 in FIG. 1) on the plurality of convolutionally encoded symbols.

[0060] The method 500 includes, at operation 540, providing the plurality of polar encoded symbols for transmission or storage.

[0061] FIG. 6 is a flowchart for improving an error correction capability of an decoder. The method 600 includes, at operation 610, receiving a noisy codeword, the codeword having been generated based on an outer stream decodable code and an inner polar code and provided to a communication channel or a storage channel prior to reception by the decoder, the stream decodable code characterized by a trellis. In an example, FIG. 1 illustrates the concatenated code that includes the outer stream decodable code (110) and the inner polar code (120).

[0062] The method 600 includes, at operation 620, performing, based on the trellis, a list decoding operation on the noisy codeword vector to generate a plurality of information symbols, the list-decoding operation being configured to traverse through a plurality of states at one or more stages of a plurality of decoding stages.

[0063] In some embodiments, an z-th symbol of any noisy codeword of the outer stream decodable code could be decoded to a valid symbol based on a first i+w symbols of the noisy codeword, wherein each codeword of the outer stream decodable code has a length of n symbols, with n > i +w, and wherein //, z, and w are positive integers. In an example, and as illustrated in FIG. 1, the outer stream decodable code may be a convolutional code, and w may be configured to be five times the constraint length of the convolutional code.

[0064] In some embodiments, the stream decodable code is a convolutional code.

[0065] In some embodiments, w = 5 x K, wherein K is a constraint length of the

convolutional code, and wherein K is a positive integer.

[0066] In some embodiments, the convolutional code is a high-rate convolutional code with a code rate greater than 1/2.

[0067] In some embodiments, the high-rate convolutional code is generated by applying a time-varying puncturing pattern to a low-rate convolutional code with a code rate < 1/2.

[0068] In some embodiments, the method 600 further includes the operation of configuring the list-decoding operation to traverse a single most probable path at each state at each stage.

[0069] In some embodiments, the method 600 further includes the operation of configuring the list-decoding operation to track L most likely paths at each stage, wherein Z is a list-size of the list-decoding operation.

[0070] In some embodiments, the polar encoding operation comprises multiplying an output of the encoding operation for the stream decodable code by a generator matrix (G).

[0071] In some embodiments, the generator matrix is defined as

[0072] Herein, denotes a Kronecker product, i? is an n x n bit-reversal permutation matrix, n = 2 ^m is a length of the polar code, and m and n are integers.

[0073] In some embodiments, the trellis is a time-varying trellis. In an example, a convolutional code with a time-varying trellis may be used to better balance out the secondary error protection over the unfrozen bit-channels of a polar code.

[0074] In some embodiments, the trellis is a time-invariant trellis.

[0075] FIG. 7 is a block diagram representation of a portion of an apparatus that can accommodate some embodiments of the presently disclosed technology. An apparatus 705, such as a base station or a wireless device (or UE), can include processor electronics 710 such as a microprocessor that implements one or more of the techniques (including, but not limited to, methods 500 and 600) presented in this document. The apparatus 705 can include transceiver electronics 715 to send and/or receive wireless signals over one or more communication interfaces such as antenna(s) 720. The apparatus 705 can include other communication interfaces for transmitting and receiving data. Apparatus 705 can include one or more memories (not explicitly shown) configured to store information such as data and/or instructions. In some implementations, the processor electronics 710 can include at least a portion of the transceiver electronics 715. In some embodiments, at least some of the disclosed techniques, modules or functions are implemented using the apparatus 705. In some embodiments, the disclosed technology can be implemented as part of a computer system (e.g., a personal computer, a smartphone, a tablet or the like) to enable improved access to data stored on a memory device associated with the computer system. The disclosed embodiments provide enhanced error correction capabilities, which improve the reliability of data stored and accessed in the computer system; at the same time, these enhancements are achieved by reduced computational complexity of the operations compared to existing techniques.

[0076] It is understood that the various disclosed embodiments may be implemented individually, or collectively, in devices comprised of various components, electronics hardware and/or software modules and components. These devices, for example, may comprise a processor, a memory unit, an interface that are communicatively connected to each other, and may range from desktop and/or laptop computers, to mobile devices and the like. The processor and/or controller can perform various disclosed operations based on execution of program code that is stored on a storage medium. The processor and/or controller can, for example, be in communication with at least one memory and with at least one communication unit that enables the exchange of data and information, directly or indirectly, through the communication link with other entities, devices and networks. The communication unit may provide wired and/or wireless communication capabilities in accordance with one or more communication protocols, and therefore it may comprise the proper transmitter/receiver antennas, circuitry and ports, as well as the encoding/decoding capabilities that may be necessary for proper transmission and/or reception of data and other information.

[0077] Implementations of the subject matter and the functional operations described in this patent document can be implemented in various systems, digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Implementations of the subject matter described in this specification can be implemented as one or more computer program products, i.e., one or more modules of computer program instructions encoded on a tangible and non-transitory computer readable medium for execution by, or to control the operation of, data processing apparatus. The computer readable medium can be a machine- readable storage device, a machine-readable storage substrate, a memory device, a composition of matter effecting a machine-readable propagated signal, or a combination of one or more of them. The term“data processing unit” or“data processing apparatus” encompasses all apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, or multiple processors or computers. The apparatus can include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of them.

[0078] A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

A computer program does not necessarily correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (e.g., files that store one or more modules, sub programs, or portions of code).

A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a

communication network. [0079] The processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., FPGA (field programmable gate array) or ASIC (application specific integrated circuit).

[0080] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read only memory or a random access memory or both. The essential elements of a computer are a processor for performing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto optical disks, or optical disks. However, a computer need not have such devices.

Computer readable media suitable for storing computer program instructions and data include all forms of nonvolatile memory, media and memory devices, including by way of example semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory devices. The processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

[0081] While this patent document contains many specifics, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as descriptions of features that may be specific to particular embodiments of particular inventions. Certain features that are described in this patent document in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple

embodiments separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

[0082] Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Moreover, the separation of various system components in the embodiments described in this patent document should not be understood as requiring such separation in all embodiments.

[0083] Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.