BACKGROUND Semiconductors are used in integrated circuits for electronic applications, including radios, televisions, cell phones, and personal computing devices, as examples. One type of semicon- ductor device is a semiconductor storage device, such as a dy- namic random access memory (DRAM) and flash memory, which uses a charge to store information.

Spin electronics, which combines semiconductor technology and magnetics, is a more recent development in semiconductor memory devices. The spin of an electron, rather than the charge, is used to indicate the presence of a"1"or"O". One such spin electronic device is a resistive memory device referred to as a magnetic random access memory (MRAM), which includes conductive lines positioned perpendicular to one another in different metal layers, the conductive lines sandwiching a magnetic stack which functions as a memory cell. The place where the conduc- tive lines intersect is called a cross-point. A current flow- ing through one of the conductive lines generates a magnetic field around the conductive line and orients the magnetic po- larity of one layer of the magnetic stack. A current flowing through the other conductive line induces the magnetic field and can partially turn the magnetic polarity, also. Digital information, represented as a"0"or"1", is storable in the alignment of magnetic moments in the magnetic stack. The re- sistance of the magnetic stack depends on the moment's align- ment. The stored state is read from the magnetic stack by de-

tecting the component's resistive state. An array of memory cells may be constructed by placing the conductive lines in a matrix structure having rows and columns, with the magnetic stack being placed at the intersection of the conductive lines.

An advantage of MRAMs compared to traditional semiconductor memory devices, such as DRAMs, is that MRAMs are non-volatile.

This is advantageous because a personal computer (PC) utilizing MRAMs would not have a long"boot-up"time as with conventional PCs that utilize DRAMs, as an example.

Figure 1 illustrates a magnetic tunnel junction (MTJ) stack that comprises a resistive or magnetic memory cell. The terms "memory cell"and"MTJ stack"are used interchangeably herein and refer to the MTJ shown in Figure 1. The MTJ comprises two ferromagnetic layers MI and M2 that are separated by a tunnel layer TL. The MTJ stack is positioned at the cross-point of two conductors, referred to as a wordline WL and a bitline BL.

One magnetic layer M1 is referred to as a free layer, and the other magnetic layer M2 is referred to as a fixed layer. The magnetic orientation of the free layer M1 can be changed by the superposition of the magnetic fields caused by programming cur- rent IBL that is run through the bitline BL and the programming current IwL that is run through the wordline WL. A bit, e. g., a"0"or"1", may be stored in the MTJ stack by changing the orientation of the free magnetic layer relative to the fixed magnetic layer. If both magnetic layers M1 and M2 have the same orientation, the MTJ stack has a low resistance Rc. The resistance Rc is higher if the magnetic layers have opposite magnetic orientations.

In some MRAM memory array designs, the MTJ stack is combined with a select transistor X1, as shown in Figure 2, which is a cross-sectional view of a 1T1MTJ design (one transistor and one MTJ stack). A schematic diagram of the MTJ stack and select transistor X1 is shown in Figure 3. A bitline BL is coupled to

one side of the MTJ stack, and the other side of the MTJ stack is coupled to the drain D of a select transistor X1 by metal layer MX, via VX, and a plurality of other metal and via lay- ers, as shown. The source S of the transistor X1 is coupled to ground (GND). Xl may comprise two parallel transistors that function as one transistor, as shown in Figure 2. Alterna- tively, X1 may comprise a single transistor, for example. The gate G of the transistor X1 is coupled to a read wordline (RWL), shown in phantom, that is preferably positioned in a <BR> <BR> different direction than, e. g. , perpendicular to, the bitline BL direction.

The select transistor X1 is used to access the memory cells MTJ. In a read (RD) operation during current sensing, a con- stant voltage is applied at the bitline BL. The select tran- sistor X1 is switched on, e. g. , by applying a voltage to the gate G by the read wordline RWL, and current then flows through the bitline BL, the magnetic tunnel junction MJT, over the MX layer, down the metal and via stack, through the transistor drain D, and through the transistor XI to ground GND. This current is then measured and is used to determine the resis- tance of the MJT, thus determining the programming state of the MJT. To read another cell in the array, the transistor X1 is switched off, and the select transistor of the next cell is switched on.

The programming or write operation is accomplished by program- ming the MTJ at the cross-points of the bitline BL and program- ming line or write wordline WWL using selective programming currents. For example, a first programming current ILL passed through the bitline BL causes a first magnetic field component in the MJT stack. A second magnetic field component is created by a second programming current IWL that is passed through the write wordline WWL, which may run in the same direction as the read wordline RWL of the memory cell, for example. The super-

position of the two magnetic fields produced by programming currents IBL and IWL causes the MJT stack to be programmed. To program a particular memory cell in an array, typically a pro- gramming current is run through the write wordline WWL, which activates all cells along that particular write wordline WWL.

Then, a current is run through one of the bitlines, and the magnetic field switches only the MJT stack at the cross-point of the write wordline WWL and the selected bitline BL.

The resistance difference between programmed and unprogrammed MRAM memory cells is relatively small. For example, the MJT may be in the order of a 10k ohm junction, and there is a change of about 20% in the resistance when a magnetic field is applied at the MJT. This changes the sense value from 10k ohm <BR> <BR> to between about 6 to 8k ohm, e. g. , 7k ohm. For other memory devices such as flash memory cells or static random access mem- ory (SRAM) cells, there is a larger resistance difference be- tween programmed and unprogrammed memory cells than in MRAMs.

For example, if a flash cell is activated, the"on"resistance is about 5k ohms, and the"off"resistance is infinite. While other types of memory cells completely switch on or off, an MRAM cell only has a small change in the resistance value upon programming. This makes MRAM cell sensing more difficult.

Either current sensing or voltage sensing can be used to detect the state of memory cells. DRAMs usually are sensed using voltage sensing, for example. In voltage sensing, the bitline <BR> <BR> is precharged, e. g. , to 1 volt, with the memory cell not acti- vated. When the memory cell is activated, the memory cell charges or discharges the bitline and changes the voltage of the bitline. However, in some types of memory cells, the mem- ory cell is small, and the bitline length may be long, e. g., may extend the entire width of the chip. The memory cell may not be able to provide enough cell current to discharge or charge a large bitline capacity within a required time. This

results in an excessive amount of time being required to read the memory cells. Therefore, voltage sensing is not a pre- ferred choice of sensing scheme for some memory devices, such as MRAM devices.

Current sensing may be used to detect a resistance change of resistive memory cells. Current sensing is the desired method of sensing the state of MRAM cells, for example. In current sensing, a voltage is applied to the bitline, and the bitline voltage is kept constant with a sense amplifier. The cell cur- rent is directly measured, with the cell current being depend- ent on the resistance of the memory cell being read. The use of current sensing reduces the capacitive load problem from long bitlines that may occur in voltage sensing.

In MRAM device current sensing, a voltage is applied to the bitline, and the current change at the bitline due to the re- sistance change of the magnetic tunnel junction is measured.

However, because the resistance difference between a programmed and unprogrammed cell is small in MRAM memory cells, the cur- rent difference sensed is also smaller than the current change from a flash or an SRAM cell, for example. What is needed in the art is an improved current sensing design for memory de- vices.

SUMMARY OF THE INVENTION Embodiments of the present invention achieve technical advan- tages as a current sense amplifier that is particularly useful in sensing current in resistive memory devices. A symmetrical high-speed current sense amplifier is disclosed that comprises complementary reference cells and configurable sensing paths that eliminate architecture-related capacitive mismatch contri- butions. The current sense amplifier is adapted for use in a symmetric sensing architecture, and includes at least one cur- rent mirror that may be configured using switching transistors,

or a multiplexer may be, used to select the input signal that is connected to the first or second side of the current mirror.

In accordance with a preferred embodiment of the present inven- tion, a current sense amplifier includes a voltage comparator having a first input, a second input and an output, and a first clamping device coupled between the first input of the voltage comparator and a first input signal. A second clamping device is coupled between the second input of the voltage comparator and a second input signal. The first clamping device and the second clamping device are coupled to a reference voltage. A configurable current mirror is coupled between the first and second input of the voltage comparator.

In accordance with another preferred embodiment of the present invention, a current sense amplifier includes a voltage com- parator having a first input, a second input and an output, and a first clamping device coupled between the first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage com- parator and a second input signal, the second clamping device being coupled to the reference voltage. The current sense am- plifier includes a current mirror having a first side and a second side, the current mirror first side including a first transistor coupled between a voltage source and the first clamping device and the current mirror second side including a second transistor coupled between the voltage source and the second clamping device, the first and second transistor gates being coupled together, and the gate and drain of the second transistor being coupled together. The current sense amplifier includes a multiplexer, wherein the multiplexer is adapted to select whether the first input signal or second input signal is connected to the first or second side of the current mirror.

In accordance with yet another preferred embodiment of the pre- sent invention, a memory device includes an array of memory cells, the memory cells having a first side and a second side, wherein at least two of the memory cells comprise reference cells. A plurality of parallel wordlines are coupled proximate the first side of the memory cells, the wordlines running in a first direction. A plurality of parallel bitlines are coupled proximate the second side of the memory cells. The memory de- vice includes a symmetric sensing circuit including at least one column selector and at least one current sense amplifier, the column selector being coupled to the memory array and com- prising at least one column select transistor coupled to each bitline in the array. The current sense amplifier includes a voltage comparator, a first clamping device, a second clamping device, and a current mirror having a first side and a second side. The voltage comparator includes a first input, a second input and an output. A first input signal is coupled to the voltage comparator first input, a second input signal is cou- pled to the voltage comparator second input, and the first and second input signals comprise either current from a selected memory cell or current from at least one reference cell. The voltage comparator outputs a logic state of the selected memory cell.

Another preferred embodiment of the invention is a method of sensing current. The method includes providing a first tran- sistor and a second transistor, providing a first input signal having a first voltage and a first current, and clamping the first voltage and passing the first current to the first tran- sistor. The method includes providing a second input signal having a second voltage and a second current, and clamping the second voltage and passing the second current to the second transistor, wherein the first input signal and second input signal comprise either current from a selected memory cell or current from at least one reference cell. The method includes

selectively mirroring the first or second current from the first or second transistor to the second or first transistor, and comparing the voltage across the first or second transistor to the voltage across the second or first transistor, wherein selectively mirroring the current amplifies the voltage differ- ence between the voltage across the first transistor and the voltage across the second transistor.

Advantages of embodiments of the present invention include in- creased performance and speed in reading information stored in memory devices. Capacitive load devices may be used to in- crease performance and balance capacitive loads. The configur- able current mirror may be achieved by using select transis- tors, or a multiplexer may be used to select the input signal that is connected to the first or second side of the current mirror. In one embodiment, one of two transistors of the cur- rent mirror is selectable to function as a transistor diode.

In another embodiment, the transistors of the current mirror are hard-wired but the input signal that is connected to the first or second side of the current mirror is selected by a multiplexer in the sense amplifier input path.

The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that fol- lows may be better understood. Additional features and advan- tages of embodiments of the invention will be described herein- after which form the subject of the claims of the invention.

It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the

spirit and scope of the invention as set forth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying draw- ings, in which: Figure 1 shows a perspective view of an MTJ stack ; Figure 2 shows a cross-sectional view of an MRAM memory device having a select FET; Figure 3 is a schematic diagram of the device shown in Figure 2; Figure 4 is a schematic of an asymmetric sensing circuit that averages the current of two reference cells; Figure 5 is a schematic of a symmetric sensing circuit having two differential amplifiers; Figure 6 shows a current sense amplifier in accordance with an embodiment of the present invention that includes a voltage comparator, bitline clamping devices, and a configurable cur- rent mirror ; Figure 7 shows a current sense amplifier in accordance with an embodiment of the present invention, having a cascode sense am- plifier design, bitline clamping devices, and a configurable current mirror ; Figure 8 shows an embodiment of the present invention with a fixed/hard-wired current mirror and having multiplexing devices between the bitline clamp devices and the sense lines at the sense amplifier inputs;

Figure 9 illustrates an embodiment having a fixed/hard-wired current mirror and a multiplexer between the clamping devices and the inputs of the voltage comparator; Figure 10 shows an embodiment similar to those shown in Figures 8 and 9, wherein the clamping devices function as a multi- plexer ; Figure 11 illustrates a current sense amplifier in accordance with another embodiment of the present invention that includes additional dummy capacitive devices to provide balanced ca- pacitive loads ; Figure 12 shows a current sense amplifier in accordance with yet another embodiment of the present invention that includes dummy capacitive devices disposed on the side of the sense am- plifier that has no gate capacitance; Figure 13 shows an architecture for an MRAM device in which em- bodiments of the present invention may be implemented; and Figure 14 shows a schematic diagram of an embodiment of the in- vention implemented in an MRAM design.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illus- trative of specific ways to make and use the invention, and do not limit the scope of the invention.

Embodiments of the present invention will be described with re- spect to preferred embodiments in a specific context, namely a FET MRAM device. The invention may also be applied, however,

to resistive memory devices and other memory devices that use a current sense amplifier to detect the resistive state of memory cells. The current sense amplifier is also applicable in other applications where an unknown current is compared to a refer- ence current in order to read or sense the unknown current.

In resistive memory devices such as MRAMs, current sensing cir- cuits may be either asymmetric or symmetric. An asymmetric sense amplifier scheme 11 is shown in the prior art drawing of Figure 4. Shown is an example for a current sensing scheme 11 for a 1T1MTJ memory cell using averaging of reference cells RC and RC2 to produce a reference current. The current sensing scheme 11 comprises a current sense amplifier 12 and a column selector 14 coupled to a memory array 16.

Only one memory cell 10 is shown; however, there may be hun- dreds or thousands of memory cells in the array 16. The refer- ence cells RCl and RC2 preferably reside in the array with the memory cells 10, but the reference cells RC1 and RC2 may alter- natively reside in another array 16, for example. Reference cell RC1 may comprise a cell programmed as a logic 1, and ref- erence cell RC2 may comprise a cell programmed as a logic 0, for example. Each bitline BL containing a memory cell 10 is connected to at least one column select transistor X2 of the column selector 14. The column selector 14 is connected to the sense amplifier 12. The bitline clamp transistor X3 is coupled to a multiplexer (not shown) that is coupled to a plurality of other memory cells, each via a column select transistor (also not shown). Cell 10, RCl and RC2 are located on bitlines se- lected by the column selector 14. These cells are shown as ex- amples for cells on the bitlines.

As current sensing is used in Figure 4, the selected bitlines are kept at a constant potential by bitline clamping transis- tors X3 during the read operation. The current comparator 18 compares the currents of the selected memory cell 10 with the

averaged current of reference cells RC1 and RC2. The level of the reference cell current is the approximate midpoint between the current of a selected cell with a"0"state and a selected cell with a"1"state, in MRAM applications. Alternatively, the current sense amplifier 12 may use only one reference cell, not shown, in other applications.

A read wordline RWL is coupled to the gate of the select tran- sistor X1 of the selected cell 10. If the read wordline RWL is activated, then all of the select transistors X1 in that row of the memory array 16 are switched on. The column select tran- sistor X2 of the column selector 14 is used to select the cor- rect bitline BL (e. g. , the column of the selected memory cell 10). The column selector 14 switches the bitline BL of the se- lected cell to the direction of the sense amplifier 12. The current sense amplifier 12 reads the resistive state of the se- lected cell 10 by measuring the current. The current sense am- plifier 12 comprises a current comparator 18 coupled to tran- sistor X3 and transistors X3R1 and X3R2 of the reference paths for reference cells RCl and RC2. The current sense amplifier 12 maintains a constant bitline BL voltage during a read opera- tion, using transistors X3 that are coupled to the signal"BL clamp voltage. "Transistors X3 typically comprise source- follower transistors, for example. The current comparator 18 compares the current through transistor X3 of the selected cell 10 with the average of the currents through X3R1 and X3R2 of the reference cells, to determine the resistive state of selected cell 10, which information is output (indicated by"DATA OUT") as a digital"1"or"0"at node 20 of the current sense ampli- fier 12.

The sensing scheme 11 shown in Figure 4 is disadvantageous in that it has an asymmetric structure. Two bitlines for only two reference cells RC1 and RC2 and column selector switches X2R1, X2R2 are connected to the right side (the negative input) of

the comparator 18, while only one bitline and a large number of column selector switches X2 are connected to the left side (the positive input) of the current comparator 18 of the current sense amplifier 12. For example, there may be one out of 64 bitlines of memory cells 10 coupled to the positive input of the current comparator 18, and two bitlines for reference cells coupled to the negative input of the current comparator 18.

Because of this asymmetry, the capacitive load of the sensing path at the positive input of the current comparator 18 is much different from the capacitive load of the reference path at the negative input of the current comparator 18. The capacitive load comprises the capacitance of the switching transistors X3, X3R1 and X3R2, and the metal lines capacitively loaded by the memory cells, e. g. , the bitlines BL. This makes the circuit sensitive to many noise sources coupled into the circuit during sensing, such as power supply noise, internal asymmetric cou- pling of switching noise, as examples, and also increases the sensing time because of different RC time constants of the sensing paths for the selected memory cell and reference cells.

Mismatches in the sensing path of an MRAM memory device tend to be the main performance limiters for the array read access time.

A symmetric sensing scheme or circuit 24 for MRAM FET memory devices is shown in Figure 5, which avoids the problems of the asymmetric sensing scheme 11 shown in Figure 4. With a symmet- ric sensing circuit 24 such as the one shown, the inputs of the comparators 19 and 22 have approximately equal effective ca- pacitive loads. No matter which bitline is read, the wiring of the sensing path and effective capacitive load are approxi- mately equal at each input, which eliminates or reduces error voltages and noise. The reference path has twice the load of the sensing path, but the reference path is connected to two sense amplifier inputs (the negative inputs of comparators 19 and 22). Therefore, the RC constant in both sense amplifier

paths is equal, and therefore the effective capacitive load is equal. The memory array 16 is not shown in Figure 5; however, a memory array 16 is coupled to the column selector 14, as shown in Figure 4.

The current sense amplifier 12 comprises a first and second voltage comparator 19 and 22, each having an output 20 and 26.

The load devices XL1, XL2, XL3, and XL4 preferably comprise tran- sistors, the load devices being the same type of devices (e. g., having the same load characteristics). Half of the select transistors X231, X23o.... X2l6, X2R1 (and corresponding memory cells 10 in the array 16) along the bitlines BL<31> through BL<16>, refBL<1> are coupled to the first voltage comparator 19, and the other half of the select transistors X2R2, X215...

X21, X2o are coupled to a second voltage comparator 22. In this scheme 24, both sides of each current comparator 19 and 22 have the same transient behavior because of the equal effective capacitive and resistive loads on the first and second voltage comparators 19 and 22. While 16 bitlines are shown on each side in Figure 5, there may be more bitlines, e. g. , 32 or 64, as examples.

For comparator 19, odd bitlines BL<31> through BL<17> are cou- pled to a masterline ML3 by corresponding column select tran- sistors X231 through X217, and even bitlines BL<30> through BL<16> are coupled to a masterline ML2 by corresponding column select transistors X230 through X216. Similarly, for comparator 22, odd bitlines BL<15> through BL<1> are coupled to a master- line ML1 by corresponding column select transistors X215 through X2l, and even bitlines BL<14> through BL<0> are coupled to a masterline MLO by corresponding column select transistors X214 through X2o. Therefore, the capacitive load of the bitli- nes is distributed half to the lower masterlines ML3 and ML1 and half to the upper masterlines MLO and ML2. If an odd bitline is selected, the capacitive load is distributed to a

lower masterline ML3 or ML1, for example. The reference bitli- nes refBL<l> and refBL<2> may be coupled either to the master- line ML3 or ML2, or ML1 or MLO, respectively (whichever is not being used by the selected cell), using-switches S5 and S6, for example.

The selection of a memory cell at bitline BL<31> will next be described. Column select transistor X231 is switched on, which connects bitline BL<31> to the lower masterline ML3. The col- umn select transistors X2R1 and X2R2 for the reference cells are switched on, and the connections 28 and 30 in switch Ss and S6, respectively, are made to the top masterlines ML2 and MLO.

Switch S2 between the top masterlines ML2 and MLO is closed in order to average the reference cell currents. Switch S1 be- tween the two lower masterlines ML3 and ML1 stays open.

In the symmetric sense circuit 24 arrangement with odd and even bitlines being connected to two separate masterlines, the ef- fective capacitive load seen at the inputs of the voltage com- parators 19 and 22 is substantially equal. In particular, the RC time constants of the sensing paths including masterline ML1 or ML3 is approximately equal to the RC time constants of the two sensing paths connected to the shorted masterline ML2/MLO.

During a read operation, the lower masterlines ML1 and ML3 have eight transistors X231, X229 to X217 and X21s, X213 to X21 and one bitline associated with the selected cell or reference cell, respectively, connected to them, and the top masterlines ML2 and MLO have eight transistors X23o, X228 to X216 and X214, X212 to X20 and one bitline associated with the selected cell or reference cell, respectively, connected to them. While the top masterlines ML2 and MLO also have reference transistors X2R1 and X2R2 connected to them, this is not a significant difference in capacitance. So, the symmetric structure produces a symmetric effective capacitive load at the inputs of the voltage compara- tors 19 and 22. Note that if a bitline is chosen that is con-

nected to a lower masterline, the reference cells should be connected to an upper masterline. Similarly, if a bitline is chosen that is connected to an upper masterline, the reference cells should be connected to a lower masterline. The connec- tion of the reference cells to the upper or lower masterlines ML2/MLO or ML1/ML3 is made by switches Ss and S6.

Next, the averaging of the two reference cell currents will be described, with reference to the current sense amplifier 12 portion of the symmetric sense circuit 24 of Figure 5. Assume for purposes of this discussion that the reference bitlines are connected to the bottom masterline ML1/ML3, and the selected cell bitline is connected to the top masterline ML2/MLO. The lower masterline switch S1 connects the two reference bitlines refBL<1> and refBL<2> together. The voltage at the reference bitlines refBL<l> and refBL<2> is kept constant by the BL clamp transistors X32 and X33. The reference current of the reference bitlines refBL<l> and refBL<2> is added due to the connection of the lower masterline switch S1. The reference bitlines refBL<1> and refBL<2> current flows through the bitline clamp- ing devices X32 and X33 and through load devices XL2 and XL3, re- spectively. The reference bitlines refBL<l> and refBL<2> cur- rent is added; it flows through two parallel resistors XL2 and XL3 to VDD. The selected cell is coupled to the top masterline ML2. Current from a selected cell (e. g., X228) flows through the BL clamping device X3, and through one load device, XL1 to VDD. The cell current causes a voltage shift at the load de- vice XL1, and the voltage comparator 19 detects this change in voltage at the load device XL1. The load device XL1 transforms the cell current into a voltage, according to Ohm's law.

To read a selected cell X228, cell current flows through the load device XL1, is transformed to a voltage, and the voltage is seen by the positive input of voltage comparator 19. At the negative input, two load devices XL2 and XL3 are connected in

parallel because switch S4 is closed, so their total resistance is half the resistance of load device XL1. The currents of the 1 reference bitline and the 0 reference bitline added together are approximately twice the current of a regular memory cell.

This current is fed into two load devices XL2 and XL3 in paral- lel, which results in half the value of a regular load device, and this divides the current by two again. Thus, the voltage that is created at the parallel connection of load devices XL2 and XL3 is the averaged voltage between a 1 and a 0 reference cell, compared with a voltage of one load device XL1.

A problem with the symmetric sensing scheme is that sometimes the top masterline ML2 is used for the sensing path (when read- ing an even bitline), and other times the bottom masterline ML3 is used for the sensing path (when reading an odd bitline).

When the bottom masterline ML3 is used for the sensing path, then the top masterline ML2 is used for the reference cells.

In this case, switch S2 is closed to connect load devices XL1 and XL4 in parallel, and the current averaging is accomplished by the load devices XL1 and XL4. A disadvantage of this sym- metric sensing structure is that a single sense amplifier can- not be used, because the averaging has to be accomplished some- times using the bottom masterline and sometimes using the top masterline. Therefore, the structure requires two voltage com- parators 19 and 22. The two voltage comparators 19 and 22 work together, achieving the averaging either using load devices XL1 and XL4 for the top masterline MLO and ML2, or alternatively, using load devices XL2 and XL3 for the bottom masterline ML1 and ML3 in order to achieve the symmetric behavior of the sensing scheme 24.

In memory circuits there are many sources of noise, such as noise from power supplies, output buffers, or internal switch- ing noise of the memory device itself, for example. In order to reduce the influence of these noise sources as much as pos--

sible, it is necessary to achieve the same RC time constants for the sensing paths from the selected bit lines to the sense amplifier 12 inputs. If voltage disturbances are introduced and there is an RC network, this will produce some voltage or current in the RC network. However, if there are two identical RC networks at the voltage comparator inputs, then these RC networks will have the same parasitic responses, and the noise essentially cancels itself out. The voltage comparators 19 and 22 then see the same parasitic response on both the positive and negative input, and they are not affected by the noise.

Therefore, for a symmetric sensing scheme 24, as shown in the example of Figure 5, a sense amplifier with a symmetric sensing structure is needed in the art, to cancel out potential noise and to achieve fast read times. If there is noise in the sense amplifier, it may take a longer amount of time to read data, because it takes a while for the unwanted capacitive effects to disperse so that the data is valid. A symmetric sensing struc- ture is needed that will cancel out the noise and thus permit faster read operations.

Embodiments of the present invention comprise a sense amplifier for use in a symmetric sense amplifier circuit such as the one shown in Figure 5. A preferred embodiment of the invention is a current sense amplifier 32 (see Figure 6) that can be config- ured to be used in a symmetric sensing concept, which is advan- tageous because high performance in MRAM memory devices may be achieved, even though the MRAM memory sensing signals are small.

Figure 6 shows a current sense amplifier 32 in accordance with an embodiment of the invention that includes a voltage compara- tor 34. The drains of bitline clamping devices T1 and T2, which preferably comprise transistors, are coupled to the posi- tive and negative inputs, respectively, of the voltage compara- tor 34. The sources of transistors T1 and T2 are connected to

a first input signal inputA and a second input signal inputB, respectively, as shown. The gates of transistors T1 and T2 are connected to a reference voltage Analog which preferably com- prises a bitline clamp voltage (see Figure 5). Reference volt- age Vanaiogi may comprise 0.7 volts, for example, although refer- ence voltage Vanalogi may alternatively comprise other voltage levels.

The current sense amplifier 32 may include optional transistors T3 and T4 which function as equalizing devices. For example, the source of transistor T3 may be coupled to signal inputB, the drain of transistor T3 may be coupled to signal inputA, the source of transistor T4 may be coupled to the negative input of the voltage comparator 34, and the drain of transistor T4 may be coupled to the positive input of the comparator 34. The gates of transistors T3 and T4 are coupled to an equalization signal EQ. Before a read operation is started, transistors T3 and T4 are activated, to ensure that the input signals inputA and inputB are at the same voltage potential (e. g. , equalized), and also to ensure that the inputs of the comparator 34 are equalized.

Advantageously, the current sense amplifier 32 includes a cur- rent mirror 36 coupled to the inputs of the comparator 34. The current mirror 36 is configurable in that it may be configured to optimize the capacitive load at the voltage comparator in- puts, e. g. , either the left side 62 or the right side 64 may be selected and activated. In this embodiment, the configurable current mirror includes a first transistor Ts coupled between a voltage source VDD and clamping device Tl, and a second transis- tor T6 coupled between the voltage source VDD and clamping de- vice T2. The gates of transistors Ts and T6 are coupled to- gether. The current mirror 36 includes a first switching tran- sistor T7 coupled between the gate and drain of transistor T5, and a second switching transistor Te coupled between the gate

and drain of transistor T6. Either of the transistors T5 or T6 may be used as a transistor diode, to be described further herein. A select signal ADDRESS is coupled to the gate of switching transistor T7, and the inverse of the select signal ADDRESS bar is coupled to the gate of switching transistor Té.

The select signal ADDRESS is adapted to activate either switching transistor T7 or T8, activating either transistor Ts or T6, respectively, as a transistor diode or current source, and amplifying the voltage difference at the first and second input of the voltage comparator 34. Transistors T5, T6, T7 and Ta preferably comprise PMOS transistors, and alternatively may comprise NMOS transistors, as examples.

When inputA has a reference current applied to it, transistor T7 of the current mirror 36 may be activated (e. g. , 0 V is ap- plied to the gate of transistor T7, to turn it on), so that transistor Ts functions as a transistor diode load device. In a transistor diode configuration, if the gate of a transistor is connected to the drain, and a current is applied to the drain, then there is a voltage to the drain, and the transistor will exhibit diode behavior. When transistor T7 is activated, the gate of transistor Ts is connected to the drain of TS, and transistor Ts is configured as a transistor diode. A current applied at inputA passes through the drain of transistor T5 which is connected to the gate of transistor T5, creating a voltage potential between the drain and source of transistor T5. This is referred to as transistor diode behavior. There is no ohmic, linear load, as in a resistor; rather, the behav- ior is that of a transistor diode, which is non-linear. The cell current from inputA is converted to a voltage by transis- tor T5 (source-drain voltage), and the voltage comparator 34 sees the positive input that has been connected at the drain of transistor T5. Similarly, transistor T6 will function as a transistor diode load device when transistor Ta is activated.

When transistor T8 is switched on, this connects the gate of T6

to the drain of T6. Current that flows into or out of inputB creates a voltage over the source-drain of the load device, transistor T6.

In accordance with embodiments of the present invention, pref- erably, switching transistors T7 and T8 are not activated at the same time, because then transistors T5 and T6 would func- tion as a transistor diode at the same time. To avoid activat- ing transistors T7 and T8 at the same time, the signal ADDRESS is applied to the gate of switching transistor T7, and an in- verse signal ADDRESS bar is applied to the gate of switching transistor TB. Preferably, signal ADDRESS is a digital sig- nal, for example, and may comprise the least significant bit (LSB) of the column addresses of the memory array 16, as an ex- ample. When signal ADDRESS is activated, switching transistor T7 is activated, and transistor Ts functions as a transistor di- ode. A current at inputA then creates a drain-source voltage at transistor T5. The drain-source voltage at transistor Ts is also the gate-source voltage at transistor Ts, because switch- ing transistor T7 is activated. Switching transistor T8 is not activated (because the gate is the inverse of the ADDRESS sig- nal), so the gate-source voltage of transistor Ts is also the gate-source voltage of transistor T6, because the gates of transistors T5 and Te are connected. Preferably, transistors Ts and T6 have the same dimensions, e. g. , comprise the same type of transistors. So, if there is a current flow at transistor Ts, the same current flows through transistors T6. Transistor Ts mirrors its current over to transistor T6, and thus the cir- cuit functions as a current mirror 36.

Now, assume that inputA is connected to the selected memory cell by a column selector (signal CS in Figure 5), and that in- puts is connected to reference cells producing an average mid- current reading. The cell current is input at inputA and is mirrored from transistor T5, creating a drain-source voltage at

transistor Ts. Since the current is mirrored into transistor T6, it flows through transistor T6. The reference current flows into inputB at the negative input of the voltage compara- tor 34. If the inputB current is a little higher than the in- putA current, this creates a large voltage shift at the nega- tive input of the voltage comparator 36. The gate voltage of transistor T6 is defined by transistor T5. Transistor T6 pref- erably operates in the saturation region, and it basically functions as a current source. If additional current is ap- plied at the drain of a transistor in the saturation region, a small shift of this current creates a large shift in the drain- source voltage, causing a large amount of voltage amplifica- tion. This amplified voltage is seen by the voltage comparator 34 negative input. This creates a large difference between the negative and positive input of the voltage comparator 34, which is advantageous. Thus, a high gain is produced, because of the mirroring of the current by the current mirror 36 from one side 64 to the other side 62, at the comparator 34.

The current sense amplifier 32 has particular advantages when used in a symmetric sensing scheme 24 shown in Figure 5. Note that the averaging of the reference currents will be done on either the left side or the right side of each amplifier in Figure 5, e. g. , either load devices XL1 and XL4 are connected together by switch S3, or load devices XL2 and XL3 are connected together using switch S4. Each load device XL1, XL2, XL3, XL4 must be a device such as a transistor that can be connected to- gether with a load device of another sense amplifier 32, if necessary. As an example, referring again to Figure 6, if a sense amplifier 32 had a hard-wired transistor diode at Ts and a current source at T6, in order to connect the first sense am- plifier 32 to another second sense amplifier 32, then the sec- ond sense amplifier should be configured so that it fits to the first sense amplifier 32. More particularly, the two transistor

diodes T5 and the two current sources T6 of the first and sec- ond sense amplifiers are coupled together.

Therefore, two sense amplifiers 32 may be used in a symmetric sensing scheme 24 as shown in Figure 5. To connect two sense amplifiers 32 together, signals ADDRESS and ADDRESS bar are switched so that the elements that are connected together are transistor diodes. Then if a transistor diode is needed on the right side 64, switching transistor T8 is activated. If a transistor diode is needed on the left side 62, switching tran- sistor T7 is activated. Advantageously, in this embodiment, either transistor Ts or T6 may be activated on either side 62/64 of the sense amplifier 32 as a transistor diode. If two sense amplifiers 32 are used in a symmetric sensing scheme, as shown in Figure 14, then in one current sense amplifier 32, switching transistor T7 can be activated, and in the other sense amplifier 32, switching transistor Te can be activated, to match the load on each side. Preferably, the comparator in- put having the reference current input to it is the side that is activated as a transistor diode, in accordance with an em- bodiment of the invention.

Referring again to Figure 6, note that transistors Tv and T8 are used for switching, to select which transistor Ts or T6 is used as the transistor diode to mirror the current, and which is used to average the reference cell current (from refBL<1> and refBL<2> of Figure 5). Thus, the switching transistors T : and Ta of the current mirror 36 provide the configurable fea- ture of the current mirror 36 in this embodiment.

To summarize the embodiment shown in Figure 6, an embodiment of the present current sense amplifier 32 includes equalizing de- vices T3 and T4, voltage clamping devices T, and T2, a voltage comparator 34, and a configurable current mirror 36. The con- figurable current mirror 36 includes two transistors Ts and T6, wherein one of the transistors Ts or T6 may be chosen to func-

tion as the transistor diode, depending on what is needed to improve the symmetry of the current sense amplifier 32 relative to the symmetric sensing architecture 24 (see Figure 5). The input signals inputA and inputB are kept at the read voltage of the memory cell by source follower clamping devices T1 and T2 that are controlled by the gate reference voltage Vanaiogi. The first and second input signals inputA and inputB preferably comprise either a current from a selected memory cell being read or a reference current of at least one reference cell (more preferably, the reference current comprises the averaged current from at least two reference cells), and the voltage comparator 34 is adapted to output (e. g., at"OUT") a logic state of the selected memory cell. Optional equalization switches T3 and T4 may be placed directly at inputA and inputB and at the positive and negative inputs of the comparator stage 34 of the sense amplifier 32. The load devices of the sense amplifier comprise a configurable current mirror 36 comprising transistors T5-T8. If ADDRESS is low and its complement high, transistors T5 and T7 form a transistor diode load of sense am- plifier input path A. Transistors T6 and T8 form a current source of the load current mirror. For ADDRESS high, the cur- rent mirror can be swapped, so that the transistor diode is at the right side 64 of the sense amplifier at inputB. Depending on which side 62/64 of the sense amplifier 32 has to be shared with another sense amplifier 32, this side of the amplifier 32 can be configured to be compatible.

In accordance with an embodiment of the invention, two or more current sense amplifiers 32 may be combined for use in a cur- rent sensing circuit, to be described further herein with ref- erence to Figure 14.

The accuracy of the configurable current mirror 36 may be im- proved by stacking additional optional cascode devices onto Ts and T6. Figure 7 shows an embodiment of the present invention

in which the current mirror switching technique is used in a cascode sense amplifier design 40. The circuit for a symmetric cascode current sense amplifier is shown. The input signals inputA and inputB are kept at the read voltage of the memory cells by clamping transistors Ti and T2. A cell current flows through these input transistors T1 and T2 can change the cur- rent balance in the left or right branch of the sense amplifier 40. The left branch comprises the current source Ces1, cascode transistor T9, and one side of the current mirror that includes transistors T5 and T-7. Similarly, the right branch comprises the current source CS2, cascode transistor Two, and one side of the current mirror 36 that includes transistors T6 and T8.

Assuming there is no current at inputA, current flows through transistor Tg, and if transistor T7 is activated, then Ts acts as a transistor diode. So, the current CSl flows through the transistor diode T5, to ground. On the right side, CSz simi- larly flows into transistor T6, but on the right side of the configurable current mirror 36, transistor T6 is configured as a current source. Therefore, there is a current mirror: tran- sistor Ts functions as a transistor diode, and transistor T6 functions as a current source. When a memory cell is connected at inputA and transistor T1 is activated, the current is changed slightly between current source CS1 and transistor TS, and the equilibrium or stable state is disturbed. This is typical of a cascode circuit-the cell current changes the current situation due to Kirchoff's law, at node 38. Similar to the embodiment shown in Figure 6, this difference in current is mirrored from transistor Ts to transistor T6, and the cur- rent difference is detected by the voltage comparator 34.

The cascode devices Tg and Two preferably comprise transistors that are coupled between the configurable current mirror 36 and the node 38 at the clamping devices T1 and T2. The gates of transistors Tg and Two are coupled to a signal Vanalog2, as shown,

which may be a voltage less than the supply voltage VDD, e. g., (VDD-1 volt). Current sources CS1 and CS2 may comprise tran- sistors being operated in the saturated region, for example.

The sources of transistor T9 and Tio are preferably at a voltage that is a threshold voltage below the voltage of Analog2.

Therefore, transistors Tg and Tie ensure that the voltage over current sources CS1 and CSZ are approximately constant, improv- ing the current source CS1 and CS2 behavior.

Using the control signal ADDRESS, the left or right side of the amplifier can be configured in order to work together with a second sense amplifier in a symmetric sensing concept, as shown in the example of Figure 6. The comparator stage 34, which converts the signals at the positive and negative inputs into a digital output signal (e. g., a"1"or"0") of the ampli- fier, e. g. , in a differential to single end conversion at sig- nal out. Equalization devices T3 and T4 as shown in Figure 6 may also be included in this embodiment. For example, a tran- sistor T4 may be coupled between the voltage comparator 34 in- puts, and a transistor T3 may be coupled between input signals inputA and inputB (not shown in Figure 7; see Figure 6).

The cascode sense amplifier 40 design is advantageous in that the capacitive behavior is improved; therefore, the cascode sense amplifier 40 may provide some speed advantages. As in the first embodiment, the configurable current mirror 36 is ad- vantageous because two current sense amplifiers 36 may be con- nected together, and the reference cell currents can be aver- aged.

Referring to Figure 7, a capacitive load asymmetry within the current sense amplifier will be described. When transistor T5 is configured as a transistor diode, the capacitive load at the drain of T5 comprises the load due to the drain of T5, the gate of transistor T5 (via the connection by transistor T7), and also the gate load of transistor T6. The capacitive load at

the drain of T6 comprises the load due to the drain of T6, no gate load because transistor Te is not activated, and a small amount of drain load from Ta. Therefore, there still remains a small amount of asymmetry of capacitance within the configur- able current mirror 36.

Figure 8 illustrates yet another embodiment of the invention, a sense amplifier 152 that is adapted for use in a symmetric sensing scheme. In this embodiment, the sense amplifier 152 comprises fixed or hard-wired current mirrors 155 (Ts and T6).

In order to maintain the ability of the sense amplifier 152 to configure itself for a symmetric sensing configuration to bal- ance the effective capacitive load of the voltage comparator inputs, multiplexing (e. g. , using a multiplexer 154 that is placed at the input of the current sense amplifier 152) of the sensing paths is used. The multiplexer 154 is adapted to se- lect whether the first input signal SLO or second input signal bSL0 is connected to the first side 162 or second side 164 of the current mirror 155.

The current sense amplifier 152 includes a voltage comparator <BR> <BR> 134 having a positive (e. g. , first) input and a negative (e. g., second) input, the voltage comparator 134 being adapted to out- put a logic state at"OUT1". A first clamping device T1 is coupled between the positive input of the voltage comparator and a first input signal SLO, the first clamping device T, be- ing coupled to a reference voltage Vanalogl. A second clamping device T2 is coupled between the negative input of the voltage comparator 134 and a second input signal bSLO, the second clamping device T2 being coupled to the reference voltage Va- nalogl. The current sense amplifier 152 includes a current mir- ror 155 having a first side 162 and a second side 164, the cur- rent mirror first side 162 including a first transistor Ts cou- pled between a voltage source VDD and the first clamping device Ti. The current mirror 155 second side 164 includes a second

transistor T6 coupled between the voltage source VDD and the second clamping device T2. The first and second transistor T5 and T6 gates are coupled together, and the gate and drain of the second transistor T6 are coupled together. A multiplexer 154 is coupled in the path of the input SLO and bSLO, as shown.

The multiplexer 154 is adapted to select whether the first in- put signal SLO or the second input signal bSL0 is connected to the first or second side of the current mirror.

When used in a symmetric sensing architecture, preferably two or more current sense amplifiers 152 are utilized as a current sensing circuit, as shown in Figure 8. The current sense am- plifiers 152 are preferably connected at transistors T6 of the current mirrors 155 of the current sense amplifiers 152. The current sense amplifiers 152 may also be connected at clamping devices T2 of the current mirrors 155 of the current sense am- plifiers 152, as shown.

In this embodiment, the multiplexing device or devices 154 is/are included between the BL clamp devices T1 and T2 and the column selector outputs (e. g. , the inputs SLO or bSL0 to the sense amplifier 152). The multiplexing device 154 changes the sense amplifier paths, and a column selector is utilized (not shown; see Figure 5) to connect the selected bitlines with the inputs of sense amplifier 152. This allows the current mirror 155 devices T6 and Ts to be"hard-wired"together. The switch- ing between a first side 162 and a second side 164 to optimize or balance the effective capacitive load of the comparator 134 is accomplished by the multiplexer device 154 located at the sense amplifier 152 inputs. The additional capacitance at the sense amplifier 152 input lines from the multiplexer devices 154 does not significantly affect the symmetric sensing scheme because the circuit 152 is relatively insensitive to parasitic effects at this node (e. g. , below the clamping devices Ti and T2).

The multiplexing devices 154 may comprise one or more NFET de- vices, PFET devices, or both, for example. As shown in Figure 8, the multiplexer 154 either connects the sense amplifier in- puts"directly"to the BL clamp devices-or reverses the connec- tion, such that the data inputs SLO/SL1 are always connected to the data sides 162 of the comparators and that the reference inputs bSLO/bSL1 are always connected to the reference side 164 of the comparators (bSA). Thus, in this embodiment, the sense amplifier 152 is configurable by the multiplexers 154. The current mirror 155 is hard-wired so that transistor T6 is a transistor diode, and transistor Ts is a current source 158.

The transistor diode T6 is used in the averaging process of the reference bitlines, which can be connected together. To con- nect them together, the multiplexer 154 selects which signal SLO/SL1 and bSLO/bSL1 goes into either the first path 162 or second path 164 of the sense amplifier 152.

An equalizing transistor T3 may be coupled between the first input signal and the second input signal, and an equalizing transistor T4 may be coupled between the inputs of the voltage comparator 134, as shown. Note that the multiplexer 154 may comprise a part of the column selector 14 (see Figure 5) rather than comprising a part of the sense amplifier 152.

In Figure 8, the multiplexer 154 adds resistance to the sensing path of the sense amplifier, which may reduce the sensed signal and may require a larger multiplexing device 154. To solve this problem, the multiplexer 160 may be disposed between the clamping devices T1 and T2 and the voltage comparator 134, as shown in the sense amplifier embodiment 166 of Figure 9. This embodiment of the sense amplifier 166 is advantageous because a smaller multiplexer 160 may be used, and the sense signal is not reduced as much. As in the other embodiments, an equaliz- ing transistor T3 may be coupled between the first input signal and the second input signal, and an equalizing transistor T4

may be coupled between the inputs of the voltage comparator, as shown. When used in a symmetric sensing architecture, refera- bly two or more current sense amplifiers 166 are utilized as a current sensing circuit, as described for the embodiment shown in Figure 8.

In another embodiment 168 of the invention, the current mirror transistors T5 and T6 of the sense amplifier are hard-wired so that one device functions as a transistor diode (T6), and the multiplexing is achieved by the clamping devices T1 and T2.

Shown in Figure 10, clamping device T, comprises at least two transistors Tla and Tlb and clamping device T2 comprises at least two transistors T2a and T2b. Transistor Tla is coupled to an analog signal V1 at its gate, to the first input signal SLO at its source, and to the positive input of the comparator 134 at its drain. The gate of transistor Tlb is coupled to an ana- log signal V2, Tlb source is coupled to Tla source, and Tib drain is coupled to the negative input of the comparator 134. Simi- larly, the gate of transistor Tza is coupled to the analog sig- nal V1, T2a source is coupled to the second input signal bSLO, and TZa drain is coupled to the negative input of the compara- tor 134. The gate of transistor T2b is coupled to the analog signal V2, T2b source is coupled to T2a source, and T2b drain is coupled to the positive input of the comparator 134.

Preferably, if signal V1 is on, then signal V2 is 0. Simi- larly, if signal Vs is on (or high) then signal V, is 0. V1 and V2 are reference voltages and are preferably analog. For exam- ple, V1 and V2 may be Vanalogi (see description for Figure 6) or 0 V. A circuit (not shown) may be utilized to switch signals Vu and V2 to Vanalogi or 0. This embodiment 168 is advantageous in that no additional multiplexing devices are required. An equalizing transistor T3 may be coupled between the first input signal SLO and the second input signal bSLO, and an equalizing transistor T4 may be coupled between the inputs of the voltage

comparator, as shown. As in the other hard-wired current mir- ror embodiments 152 and 166, when used in a symmetric sensing architecture, preferably two or more current sense amplifiers 168 are utilized as a current sensing circuit.

Figure 11 shows an alternative embodiment 44 that may be used with the configurable current mirror embodiments described herein with reference to Figures 6 and 7 to reduce capacitance load asymmetry. A dummy capacitive load device 42 is coupled to the configurable current mirror 36 to achieve equal or bal- anced capacitive loads. The configurable dummy load device 42 preferably includes a first dummy transistor Tsdumm coupled be- tween the voltage source VDD and the first transistor Ts of the current mirror, and a second dummy transistor T6dum coupled be- tween the voltage source VDD and the second transistor T6 of the current mirror 36, wherein the gate of the second dummy transistor T6d is coupled to the gate of the first dummy transistor Tsd=m. The dummy load circuit 42 also includes a first dummy select transistor Tydumm coupled between the first transistor Ts of the current mirror 36 and the gate of the first dummy transistor Tod=, the gate of the first dummy se- lect transistor Tpdumm being coupled to the inverse of the first select signal ADDRESS bar. The dummy load circuit 42 includes a second dummy select transistor Tgdumm coupled between the sec- ond transistor T6 of the current mirror 36 and the gate of the second dummy transistor Tgdumny the gate of the second dummy se- lect transistor Tgdmnm being coupled to the first select signal ADDRESS. Thus, the dummy circuit 42 includes configurable dummy transistors Tsdumm and T6d= and switching devices Td= and Tadumm that provide symmetric capacitive loads at the comparator 34 inputs. The dummy transistors T5d,,. and T6d. may alterna- tively also comprise capacitors, for example.

In this embodiment, if transistor Ts is configured as a tran- sistor diode, then the drain of Ts has high capacitive loads.

If ADDRESS0 is activated low, then T7d= is not activated, so the only capacitive load due to the dummy circuit 42 is the drain capacity of the T7dum, but on the right side, Tsdumm is ac- tivated, and Tgdumm connects the transistor Tsd= and Tgduinm down to the drain of T6. Therefore, the same capacitive load is seen on the right and left side of the configurable current mirror 36. With the improved matching of the capacitive load, the current sense amplifier 44 can work faster, and it makes it much easier for the voltage comparator 34 to determine the state of the selected memory cell.

During the sensing cycle, the comparator 34 input nodes (e. g., the positive and negative inputs) move towards their final value. If the two nodes have different capacitance, then the more lightly loaded side will move more quickly, creating a different signal than appears at the other input, leading to a delay in reading the true signal and hence a slower access time. A current mirror load is, by design, somewhat mismatched in capacitance in that one side includes the gate capacitance of both devices while the other side includes no gate capaci- tance. This effect can become quite noticeable as device sizes are increased in an effort to reduce device mismatch between the two devices.

A solution to this problem is shown in Figure 12, which illus- trates another embodiment 46 of the present invention. In this embodiment 46, the capacitance of the inputs of the voltage comparator 34 is matched. At least one dummy capacitive device 48 and/or 50 is included on the side that has no gate capaci- tance, as shown. In the example shown, the dummy capacitive device comprises two dummy gates 48 and 50 that are preferably the same size as the current mirror devices Ts and T6. The dummy gates 48 and 50 are coupled across the drain and source of transistor T6 of the current mirror 155, as shown. The source and drain nodes of the dummy devices 48 and 50 are con-

nected to VDD. The dummy devices 48 and 50 preferably comprise transistors, and alternatively may comprise capacitors, for ex- ample. The dummy devices 48 and 50 balance capacitive loads of the current mirror 155. In this embodiment, there are no switching transistors required: the current mirror devices T5 and T6 are hard-wired. The dummy devices 48 and 50 are pref- erably the same devices as the devices T5 and T6, to ensure that the capacitances, structure, and parasitic effects are the same. This circuit 46 results in capacitance matching of the voltage comparator 34 input nodes SA and bSA.

Figure 13 illustrates an architecture for an MRAM device, in particular, an Array Diagnostic Monitor (ADM) core architec- ture, having a 1T1MTJ cell and corresponding 128Kb core archi- tecture. The 128Kb ADM (512WWLs/RWLs x 256BLs, 8Kb x 16) pref- erably comprises eight 16Kb segments, each connected to two data I/Os. Interleaved layout gaps for RWL stitch and ground- supply for p-well and select device connection (source node) are preferably located every 16 BLs to minimize RWL RC delay and to assure a low resistive ground path. Uni-directional RWL/WWL and bi-directional BL drivers are located adjacent to the MRAM array. Four masterlines (ML) connect the read cur- rents from two reference cells and from two data cells to two current sense amplifiers 32. Two reference BLs are shared within a 32 BL wide 16Kb segment. The design features a sym- metrical high speed sensing architecture comprising switched current mirror load devices as described for embodiments of the present invention herein.

Figure 14 shows a symmetrical sensing scheme including a sym- metrical column selector, sense amplifiers and reference scheme of a 128Kb ADM in accordance with an embodiment of the present invention. Two or more current sense amplifiers 32 are util- ized in the sensing scheme shown. First and second current sense amplifiers 32 may be coupled together between transistors

Ts and T6 by connection transistors or switches Til and T12, for example. Two or more of the other current sense amplifier em- bodiments 40,44, 46,152, 166, and 168 described herein may be coupled together and utilized similarly in a symmetrical sens- ing scheme.

The column selector 14 connects the BLs of the selected memory cells (BL31-BL16, BL15-BLO) and the two reference bit lines (refBL<1>, refBL<0>) to the input nodes of the sense amplifiers SA1 and SAO. Depending on the column select signals CS15-CSO, two even or two odd BLs are selected symmetrically to the ref- erence BLs located in the middle of a 16Kb segment of the mem- ory array.

If even BLs are selected by the column selector 14, they are connected to masterlines ML2/MLO and the reference BLs refBL<1>/refBL<2> are switched to ML3/ML1. Selected odd BLs are connected to masterlines ML3/ML1 and the reference BLs refBL<1>/refBL<2> are switched to ML2/MLO, respectively. The switching of the reference BLs is controlled by column address signal CADR (e. g. , CADR is preferably driven to 1.8V for even BLs). Each masterline is also connected to one of the four sense amplifier inputs INP1/INN1 and INPO/INNO.

The symmetric structure of this interconnect network between the BLs and the sense amplifiers guarantees equal effective ca- pacitive loads of the RC networks from the selected BLs to the sense amplifier inputs. Problems such as phase mismatch at the sense amplifier inputs, Von noise and asymmetric coupling of noise sources into the sensing paths are significantly reduced by the use of embodiments of the present invention.

The reference scheme of Figure 14 uses two reference BLs refBL<1>/refBL<2> as a reference for 16 BLs (BL31-BL16) to the left and 16 BLs (BL15-BLO) to the right. The MTJ's along one of the reference BLs (RefBLl) are preprogrammed into a high re-

sistance state RH while the MTJs along the other reference BL (RefBL2) are in the low resistance state RL. The layout struc- ture of the reference BLs is identical to BLs BL31-BLO, thereby correctly representing parameter fluctuations. During read op- eration the sense amplifiers apply the same BL voltage to the BLs of the selected memory cells as applied to the two refer- ence BLs. The cell current of two reference cells along the selected RWL is averaged by the sense amplifiers and serves as midpoint current reference which is compared to the cell cur- rent of the selected memory cells.

In order to be compatible to the symmetric column selector scheme of Figure 14, two sense amplifiers 32 (SA1 and SAG) are combined. During read operation, the BL voltage is clamped to about 300mV, as an example, by the source follower transistors T, and T2. Each sense amplifier uses special current mirror loads T5, T6, T7 and T8 for conversion of the cell currents into a voltage signal, which then can be evaluated by the compara- tors 34 of each sense amplifier 32 (SA1 and SAG) and converted into a digital output signal at DO1 and DO0.

The transistors T5, T6, T7 and Ta form two configurable current mirrors 36. Signal CADR selects which side of the current mir- ror loads works as transistor diode by activating one of the complementary switches T7 or T8. Depending on the selection of even or odd BLs by the column selector 14, the connection of the reference BLs to the sense amplifier inputs changes. Using switches T7 or Ta, the sides of the sense amplifiers to which the reference BLs RefBLl and RefBLO are connected are config- ured as transistor diode load. These transistor diode loads of two sense amplifier sides are connected in parallel by the switches Tll/Tl2. The averaging of the reference cell current is done at this parallel connection of transistor diode loads.

Switches T13 and T14 may comprise transistors and are used to

short the masterlines to which the reference BLs are connected directly at the sense amplifier inputs.

Thus, an embodiment of the present invention includes a memory device as shown in Figure 14 including an array 16 of memory cells MJT, the memory cells having a first side and a second side, wherein at least two of the memory cells RH and RL com- prise reference cells. The memory device includes a plurality of parallel wordlines (not shown in Figure 14 ; see Figures 1-3) coupled proximate the first side of the memory cells MTJ, the wordlines running in a first direction, and a plurality of par- allel bitlines BL coupled proximate the second side of the mem- ory cells. The memory device includes a symmetric sensing cir- cuit 24 as described herein that includes at least one column selector 14 and at least one current sense amplifier 32, the at least one column selector 14 being coupled to the memory array 16 and comprising a column select transistor Xn coupled to each bitline in the array 16. The at least one current sense ampli- fier 32 of the symmetric sensing circuit includes a voltage comparator 34, a first clamping device T1, a second clamping deviceT2, and a current mirror 36 having a first side 62 and a second side 64, wherein the voltage comparator 34 includes a first input, a second input and an output, wherein a first in- put signal INP1 is coupled to the voltage comparator first in- put (positive input), wherein a second input signal INN1 is coupled to the voltage comparator second input (negative in- put), the first and second input signals comprising either cur- rent from a selected memory cell MTJ or an averaged current of two of the reference cells RH and RL, and wherein the voltage comparator 34 outputs a logic state of the selected memory cell MTJ.

Another embodiment of the present invention is a method of sensing current. The method may be used, for example, to sense current from memory cells of a memory device such as the one

shown in Figure 13, for example. Referring again to Figure 6, the method includes providing a first transistor Ts and second transistor T6, providing a first input signal inputA having a first voltage and a first current, clamping the first voltage (e. g. , with clamping device T1) and passing the first current to the first transistor T5. The method includes providing a second input signal inputB having a second voltage and a second <BR> <BR> current, clamping the second voltage (e. g. , with clamping de- vice T2) and passing the second current to the second transis- tor T6, wherein the first input signal inputA and second input signal inputB comprise either current from a selected memory <BR> <BR> cell (e. g. , cell 10 of Figure 4) or an averaged current from<BR> two reference cells (e. g. , reference cells RCl and RC2 of Fig- ure 4). The method includes selectively mirroring the first or second current from the first or second transistor Ts/T6 to the second or first transistor T6/T5, and comparing the voltage across the first or second transistor Ts/T6 to the voltage across the second or first transistor T6/Ts, wherein selec- tively mirroring the current amplifies the voltage difference between the voltage across first transistor Ts and the voltage across the second transistor T6.

Embodiments of the present invention achieve technical advan- tages as a current sense amplifier and memory device having a configurable current mirror, such that either the left path or right path of the current mirror may be selected. Two current sense amplifiers described herein may be used with a column se- lector of a symmetric sensing architecture, to provide a resis- tive memory device with well-matched capacitive loads, thus in- creasing the speed of the resistive memory device. The current mirror provides increased gain at the voltage comparator 34, which improves the performance of the memory device. The con- figuration of the current mirrors is preferably achieved using gate/drain switching devices that are controlled by a digital signal (for example, a simple address signal). This is advan-

tageous because the address signals of the memory array can be used to switch the current sense amplifier. The use of cascode devices further improves the capacitance and speed of the de- vice. The current mirror may be configured using switching transistors, or alternatively, the current mirror can be hard- wired and a multiplexer may be used to select the side of the current mirror to be used for a particular input signal path.

The multiplexer may be coupled at the sense amplifier inputs, or may be located between the clamping devices and the voltage comparator. The clamping devices may function as the multi- plexer in one embodiment.

Although embodiments of the present invention and its advan- tages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the in- vention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that the circuits, circuit elements, and current sensing architectures described herein may be varied while remaining within the scope of the present invention.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, ma- chine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, composi- tions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corre- sponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, ma- chines, manufacture, compositions of matter, means, methods, or steps.