Title:
CURRENT SOURCE CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2007/055248
Kind Code:
A1
Abstract:
The conventional current source circuit configuration requires a long reset time
for resetting a current source circuit from a current output stop state to a normal
operation state. A gate terminal of a first P channel MOS transistor (TR1) is connected
to an output of a bias circuit (101) outputting a predetermined value voltage
and one end of a voltage stabilizing capacity (103) while a gate terminal of a second
P channel MOS transistor (TR2) is connected to a voltage control circuit (102)
capable of controlling the output voltage according to the operation mode. With
this configuration, the second P channel MOS transistor (TR2) can be set to a non-electrically
connected state to stop the current output of a current source circuit (100).
The bias circuit (101) is set to output the same bias voltage both in a wait mode
when current output of the current source circuit (100) is in a stop state and in
a normal operation state when the current source circuit (100) is normally operating,
so that electric charge of the voltage stabilizing capacity (103) is not discharged
and the reset time from the wait mode to the normal operation mode can be reduced.
Inventors:
NODA TSUYOSHI
IKOMA HEIJI
IKOMA HEIJI
Application Number:
PCT/JP2006/322292
Publication Date:
May 18, 2007
Filing Date:
November 08, 2006
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD (JP)
NODA TSUYOSHI
IKOMA HEIJI
NODA TSUYOSHI
IKOMA HEIJI
International Classes:
G05F3/24; H03F3/345; H03K19/00
Foreign References:
| JP2004110574A | 2004-04-08 | |||
| JP2005285062A | 2005-10-13 | |||
| JP2002312043A | 2002-10-25 |
Attorney, Agent or Firm:
HAYASE, Kenichi (4F The Sumitomo Building No.2, 4-7-28, Kitahama, Chuo-ku, Osaka-sh, Osaka 41, JP)
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