Title:
D-TYPE FLIP-FLOP CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2019/235363
Kind Code:
A1
Abstract:
A D-type flip-flop circuit 1 has a configuration in which a pMOS transistor p8 and an nMOS transistor n8 are added to pMOS transistors p1-p7, p11-p15 and nMOS transistors n1-n7, n11-n15 which are provided to a typical D-type flip-flop circuit.
Inventors:
KOBAYASHI KAZUTOSHI (JP)
FURUTA JUN (JP)
YAMADA KODAI (JP)
FURUTA JUN (JP)
YAMADA KODAI (JP)
Application Number:
PCT/JP2019/021613
Publication Date:
December 12, 2019
Filing Date:
May 30, 2019
Export Citation:
Assignee:
NAT UNIV CORP KYOTO INST TECHNOLOGY (JP)
International Classes:
H03K3/3562; H01L21/822; H01L27/04
Foreign References:
| JP2017041675A | 2017-02-23 | |||
| JP2015012424A | 2015-01-19 | |||
| JP2014155163A | 2014-08-25 | |||
| JP2004064557A | 2004-02-26 |
Other References:
A.BALASUBRAMANIAN ET AL.: "RHBD Techniques for Mitigating Effects of Single-Event Hits Using Guard-Gates", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 52, no. 6, December 2005 (2005-12-01), pages 2531 - 2535
H.ZHANG ET AL.: "Temperature Dependence of Soft-Error Rates for FF designs in 20-nm Bulk Planar and 16-nm Bulk FinFET Technologies", 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS
See also references of EP 3806332A4
H.ZHANG ET AL.: "Temperature Dependence of Soft-Error Rates for FF designs in 20-nm Bulk Planar and 16-nm Bulk FinFET Technologies", 2016 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS
See also references of EP 3806332A4
Attorney, Agent or Firm:
SAEGUSA & PARTNERS (JP)
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