Data Converter and Line Driver for a Digital Data Communication System

Field of the Invention

This invention relates to a digital data com¬ munication system in which monopolar binary data is -converted to complementary bipolar form and coupled with a balanced data transmission line.

Background of the Invention

Digital data is typically generated and ma¬ nipulated in monopolar form. It is sometimes desirable to represent the data information in bipolar comple- mentary form for transmission from one point to another over a balanced two wire data link.

Summary of the Invention

A principal feature of the invention is a data converter having inputs of monopolar binary digital data and a clock signal at twice the data fre¬ quency, and an output of complementary bipolar data with intervals between data pulses.

More particularly, it is a feature of the data converter that it includes first and second two input NAND gates each having one input connected with the clock signal source, the first NAND gate having uninverted data connected with its other input and the second NAND gate having inverted data connected with its other input. The outputs of the NAND gates are complementary, monopolar data signals at the clock frequency and with intervals between pulses. First and second bipolar differential operational amplifiers have

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inverting and noninverting inputs cross-coupled to the outputs of the NAND gates, the outputs of the opera¬ tional amplifiers being complementary bipolar data signals with intervals between data pulses. Another feature of the converter is that each of the NAND gates has an open collector output circuit. A resistor is connected in series with the NAND gate output circuit across a DC voltage source forming a voltage divider establishing the voltage level of the data signals at the NAND gate outputs.

Still another feature is the provision of low pass filters which establish the rise and fall times of the data signals and the high frequency limit for the data. • And another feature is the provision of volt¬ age buffer amplifiers connected between the outputs of the operational amplifiers and the data transmission line.

Further features and advantages will readily be apparent from the following specification and from the drawings.

Brief Description of the Drawings

Figure 1 is a schematic diagram of a data con¬ verter illustrating the invention; and

Figure 2 are signal waveforms useful in de¬ scribing the operation of the data converter.

A binary digital data signal in monopolar form provides the data input for the data converter disclosed herein. A typical monopolar data signal is shown in Figure 2b, representing the- binary digits 011001. A clock signal. Figure 2a, with a frequency twice that of the data, is the other input to the con- verter.

The data converter. Figure 1, has two signal channels 20, 40 each with the same arrangement of ele¬ ments. The active elements are two input TTL NAND gates 21, 41, bipolar operational amplifiers 22, 42 and bipolar voltage buffers 23, 43. The outputs of the voltage buffers are connected with a balanced, two-wire data link.

The data signal. Figure 2a, from a suitable source (not shown) is connected with one input of the first NAND gate 21. The data signal is also connected with an inverter 50 and the inverted data connected with an input of second NAND gate 41. A clock signal. Figure 2a, at a frequency twice that of the data is connected with the other input of each of the NAND gates 21, 41. The outputs of the NAND gates are designated COl and CO0 respectively and are shown in Figures 2d, 2e. These signals represent the data and inverted data respectively in monopolar binary digital form at the clock frequency. Dead time intervals between the data pulses are at a zero signal level.

The NAND gate outputs COl and CO0 are cross- coupled to the inputs of the bipolar differential opera¬ tional amplifiers 22, 42. More particularly, NAND gate output signal COl is connected with the inverting input of operational amplifier 22 and with the noninverting input of operational amplifier 42. Conversely, the signal CO0 from NAND gate 41 is connected with the in¬ verting input of operational amplifier 42 and the nonin¬ verting input of operational amplifier 22. The outputs of the operational amplifiers

22, 42 are bipolar complementary waveforms coupled to voltage buffers 23, 43 which have outputs CO+ and CO-, Figures 2f and 2g respectively. These signals are connected with the data link. The voltage buffers

vide isolation but do not change the form of the sig¬ nals.

The operation of differential operational amplifiers 22, 42 will be apparent from a consideration of the input and output signal waveforms. With a data zero the inverting input of amplifier 22 is low and the noninverting input is high. The output of amplifier 22 is high and the output of voltage buffer 23, Figure 2b, is low. The inputs to differential amplifier 42 are reversed, with the noninverting input low and the in¬ verting input high. The output of differential ampli¬ fier 42 is low and the output CO- of voltage buffer 43 is high. With a data 1, the input and output signal conditions are reversed. During the dead time interval between data pulses both inputs to the bipolar differ¬ ential amplifiers 22, 42 are low and the outputs of both the differential amplifiers and the voltage buffers are 0.

The output stages of NAND gates 21, 41 are open collector transistor circuits as indicated by the broken line connection from NAND gate 21 to the collec¬ tor element of transistor 24, the emitter of which is returned to ground through resistor 25. A DC power source, as +5V, is connected through resistor 26 with the NAND gate output and thus is in series with tran¬ sistor 24 and emitter resistor 25. When transistor 24 conducts, a low condition for the NAND gate output, the output voltage level is determined by the five volt supply and the voltage divider of resistors 25, 26. This circuit configuration establishes the voltage level for signals COl and CO0 which are appropriate to develop the desired signal amplitudes CO+ and CO- at the outputs of differential operational amplifiers 22, 42 and buffer amplifiers 23, 43.

Both signal channels incorporate low pass filters only those in channel 20 will be described. Series resistor 27 and the shunt connected parallel combination of resistor 28 and capacitor 29 form a low pass filter with a time constant established pri¬ marily by capacitor 29. This filter is the -principal element in establishing the rise and fall times of the signal CO+. A second low pass filter is provided by the RC feedback network of resistor 31 and capacitor 32 connected from the output of operational amplifier 22 to the inverting input. This filter limits the high frequency response of the data converter. Both filters contribute to stability of the data converter. Voltage buffer 23 connected in the CO+ signal channel 20 between the output of operational amplifier 22 and the data link is a bipolar circuit connected across the positive and negative terminals of a DC power supply. Resistors 34, 35 in the power supply connections limit the current to the amplifier in the event of a short circuit or other fault condi¬ tion of the data link. The voltage buffer has a high input impedance and the capability of providing a high output current. It establishes an appropriate load for the operational amplifier and isolates the operational amplifier from the data link which may be highly capacitive. Voltage buffer 43 serves the same func¬ tion in the CO- signal channel 40.