DATA ERASURE VERIFICATION FOR THREE-DIMENSIONAL NONVOLATILE MEMORY

WIPO Patent Application WO/2022/188674

A1

Disclosed in the present application are a data erasure verification method for a three-dimensional nonvolatile memory, a data erasure method for the three-dimensional nonvolatile memory, and the three-dimensional nonvolatile memory. The three-dimensional nonvolatile memory comprises a plurality of memory blocks comprising a plurality of hierarchies. The data erasure verification method for the three-dimensional nonvolatile memory comprises: selecting a first hierarchy which is subjected to an erasure operation in the plurality of hierarchies; and applying a first local verification voltage to a word line corresponding to the first hierarchy, so as to verify the erasure operation for the first hierarchy, wherein when full-block erasure verification is performed on the storage block corresponding to the first hierarchy, a voltage applied to the word line corresponding to the storage block is a global verification voltage, the first local verification voltage being less than the global verification voltage.

JP4044760	How to program a non-volatile semiconductor memory device
WO/2011/025731	PARTIAL SPEED AND FULL SPEED PROGRAMMING FOR NON-VOLATILE MEMORY USING FLOATING BIT LINES
WO/2011/037703	METHODS OF READING AND USING MEMORY CELLS

LEE CHANGHYUN (CN)

PCT/CN2022/078785

September 15, 2022

March 02, 2022

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YANGTZE MEMORY TECH CO LTD (CN)

G11C16/10; G11C16/14; G11C16/34

CN112908389A	2021-06-04
US20190019563A1	2019-01-17
CN111009275A	2020-04-14
US20190102104A1	2019-04-04

CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)

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