^■ BACKGROUND OF THE INVENTION ^'

The subject invention relates to data modems and more particularly to timing recovery circuits used in the receiver of such modems. The invention is par¬ ticularly concerned with timing recovery circuits of the so-called envelope variety- Derivation of timing at a data modem receiver is, of course, a critical function, and development of a signal with particular accuracy as far as synchronism with the transmitter timing is highly desirable. More¬ over, in today's microprocessor-based mode s, it is- highly desirable to implement a timing recovery scheme which minimizes the number of microprocessor operations required.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide an improved timing recovery scheme for a data modem.

It is a- more particular object of the inven¬ tion to provide a clock extraction circuit providing a timing error signal in such a timing recovery circuit. it is yet another object of the invention to

^* provide such a scheme directed to digital implementation which provides accurate timing with a reduced number of microprocessor operations.

- - These and other objects are accomplished according to the invention by provision of a clock extraction circuit employing a filter at the input of a data modem receiver which has a periodic characteristic.

5 The periodic filter provides inputs to a squaring cir¬ cuit-means. The squaring circuit means supplies outputs to a sampling filter whose output is filtered to provide ^' the requisite error signal. This signal inputs to a phase-locked timing generator which generates sample and 0 symbol rate clocks.

BRIEF DESCRIPTION OF THE DRAWINGS

The preferred embodiment of the just- summarized invention will now be described in detail in 5 conjunction with the drawings of which:

Figure 1 is a block diagram of a timing

- recovery scheme according to the preferred embodiment.

^** Figure 2 is a schematic diagram of the clock extractor circuit of Figure 1. 0 ^" Figure 3 is an amplitude vs frequency

^" characteristic useful in illustrating the preferred embodiment. ^' . .. Figure 4 shows a generalized filter character¬ istic suitable for use with the preferred embodiment. _. Figure 5 is a flowchart illustrating micro¬ processor implementation of the preferred embodiment.

- DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

- The timing recovery scheme of the preferred embodiment is illustrated in Figure 1. The circuit includes a clock extraction circuit 11 and a timing generator 13.

The preferred relationship of these ele¬ ments 11, 13 in a modem receiver is indicated by Figure 1. The clock extraction circuit receives the

input signal to the data modem after a digital-to-analog converter 16 which samples the input signal 15. The sampling gate may be preceded by an antialiasing filter 17 and automatic gain control circuitry (not ■5 shown). The output of the sampler 15 feeds a filter 19, which ^' is a digital type. The output of the filter 19 supplies an input to other detection apparatus 21, which . ^• - may contain an adaptive equalizer means. As shown, the ^' timing generator 13 provides a clock at the sample rate 0 to the converter 15 and a clock at the symbol rate used for clocking outputs of the filters 19 and elsewhere in timing operation of the receiver. The sample clock rate is typically faster than the symbol clock, for example 9600 Hz and 1600 Hz respectively. 5 Figure 2 illustrates in detail the clock extraction circuit of Figure 1. This circuit includes an energy restricting filter 23, a ^" squaring circuit 25, a sampling filter 27 and a low pass filter 29. The energy restriction filter 23 is of a type known as a 0 periodic filter. It is shown as including a 24 sample delay element 31 and a summer 33. This is particularly suited for a 1600 baud, 1800 carrier, 50% raised cosine -system. In operation, a sample delayed 24 sample times by delay element 31 is subtracted from the current sam- 5 pie each symbol interval. The output of the summer 33 resulting from this ^' substraction is squared by the squarer 25 and fed to the input 35 of the sampling filter 27. It is noted that the delay through the clock extractor circuit 11 must equal the delay through the . ilter 19 to within an integer number of cycles.

The sampling filter 27 is shown as including a plurality of delay elements each providing a delay of 1/T seconds where T is the symbol interval. Certain of the delayed squared samples DQ ² # D^ ² , D2 ² D4 ² , D5 ² and D5 ² are summed with polarities 1, -1, -1, +1, +1, and -1

• by a summer 37. Such a sum is.,computed each symbol. The output of the summer 37 sampled at the symbol rate, is _. low passed filtered by the filter 27. The output of the sampling filter 27 is an error signal which can be 5. used to adjust a phase lock loop controlling generation of the sample and symbol clocks.

Figure 3 illustrates the nature of operation of the ^' periodic filter 23. This illustration is par¬ ticularly shown for a 1600 Hz clock derivation, for 0 example, for -a 4800 bps modem with a carrier centered at 1800 Hz and a so-called "50% raised cosine roll-off." The circuitry of Figure ^' 2 is also particularly adapted for use in such a modem.

It is known that in such a modem, the clock line is given by

CLK(w ₀ ) X(w)X (w-w ₀ )dw

—CO*- ⁷

where X(w) is the Fourier Transform (Spectrum) of the input to the squaring circuit. [The * represents co - _. . plex conjugation] and w ₀ = 2 pi • CLOCK FREQ.

If we neglect the effects of amplitude distor- tion in the transmission medium, the 50% raised cosine roll-off spectrum X.(2 pi f) at- the receiver input will be: ' - .

0. f < 600

^• cos(τr ^f ^^°) 1400 > f >_ 600

!X(2πf)| = 1 2200 > f _ 1400 cόs(τr ²² °° ^~f ) 3000 > f l 2200 0 f > 3000

O PI

As known to those skilled in the art, the regions about 2600 Hz (fj _j ) and 1000 hz (fi,) contribute clock energy independent of the data pattern. It is also known that phase distortion can be deleterious at frequencies 200 Hz or so away from f{j and f ^** -.. Finally, it is also known that it is desirable to restrict energy * at half the clock frequency. The periodic filter of the preferred embodiment has the desirable advantage of providing transmission nulls at" 200 Hz on either side of both fJJ and f. as shown in Figure 3 and of providing a null at half the clock frequency. While a periodic filter is used in the preferred embodiment, any filter providing a characteristic like the periodic filter about fjj and fj ^* . could be utilized. Thus, an arbitrary shape such as that shown in Figure 4 would suffice.

. Curve 47 in Figure 3 shows the result of com¬ puting the ^' point-by-point product of X(2ττf) and X(2τrf - w ₀ ). The amplitude of the resulting product is given by

A ,(.f,,) = cos(,2πf- ₁₆ 2 _Q 6 ₀ 00,)

in the region 2200 > f > 3000 Hz, after normalizing the maximum value to unity.

Curve 43 in Figure 3 shows the product of the amplitude response of the filter 23 with itself dis¬ placed 6y the clocking frequency. Since in this illus¬ tration the clocking frequency is a multiple of the frequency of the filter 23, the result is sin ² (T _QQ -) (after normalizing the maximum value to unity).

Curve 45 in Figure 3.shows the effect of the filter 23 on the contribution to the clocking energy. The result of passing x(t) through the filter 23 prior to ^" squaring results in an alternative point-by-point product A'(f).

Figure 5 illustrates a flow chart for imple- menting the clock extraction circuit in a microproc¬ essor. The microprocessor functions in the following discussion alluded to are well-known to those skilled in the art and will not be described in further detail herein. The flow of Figure 5 is performed once per symbol. -A s€ore denoted "W stores the 32 most recent samples outputted by the sampler 15 at a rate of, for example, 9600 samples per second. W _n is the most recent sample received. Hence, a first index IRχ is set to point to W _n , while a second index IR2 is set to point to ^ -24 _* ^A counter K is set equal to zero. Then a loop is entered where Dς = W _n - W _n -24 is calculated and stored. After calculation of one O - value, the IRχ and ^" IR2 indexes are each decremented by 1 such that the correct W values will be retrieved from the sample storage during the next iteration of the loop. The counter K = + 1 is incremented to keep track of the current iteration. Next a test is performed to ascer¬ tain whether 6 Djς's have been calculated and stored in positions denoted OQ , DJ_, D2«- D3, D4, D5. If not, the next Djς is calculated, for example Djς = W _n _ι - Wn-25** After 6 D _jς 's are calculated and stored, the clock error equation shown in block 101 are calculated. Finally, D ₀ is saved in the storage location for Dg, as it will be

C PI

used as D5 during the next symbol when the flow of Figure 5 is repeated to calculate another clock error correction value. The simplicity and speed of this routine for generating a clock error signal is apparent from Figure 5 and _^ the foregoing description.

The flow chart of Figure 5 just described illustrates a particular implementation of Figure 2 in a ^{• '} microprocessor environment. ^' A significant advantage of the invention is that calculations need only be made at the baud rate,.* thus conserving valuable microprocessor time. - -

Those skilled in the art will readily appre¬ ciate that the subject invention has numerous appli¬ cations other than in the preferred embodiment just described. Therefore, it is to be understood that, within the scope of the appended claims, the invention may be practiced other than as specifically described . herein.