Title:
DATA SAMPLING CIRCUIT, DELAY DETECTION CIRCUIT AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/060478
Kind Code:
A1
Abstract:
The embodiments of the present disclosure disclose a data sampling circuit, a delay detection circuit and a memory. The data sampling circuit comprises a first signal path and a second signal path. The first signal path is configured to receive a first signal and process and transmit the first signal. The first signal path has a first delay, and the first delay comprises a first physical delay and a compensation delay. The second signal path is configured to receive a second signal, receive the processed first signal from the first signal path, and sample the second signal according to the processed first signal. By means of the embodiments of the present disclosure, a relative delay between a first signal and a second signal can keep stable, thereby avoiding sampling failure.
Inventors:
ZHANG ZHIQIANG (CN)
Application Number:
PCT/CN2023/073884
Publication Date:
March 28, 2024
Filing Date:
January 30, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C7/10; G11C7/22; H03K5/133
Foreign References:
| CN107452415A | 2017-12-08 | |||
| CN112667024A | 2021-04-16 | |||
| CN103065677A | 2013-04-24 | |||
| US20180167061A1 | 2018-06-14 | |||
| US20070226529A1 | 2007-09-27 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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