Title:
DECODING CIRCUIT, DECODING METHOD AND SEMICONDUCTOR MEMORY
Document Type and Number:
WIPO Patent Application WO/2024/060325
Kind Code:
A1
Abstract:
A decoding circuit (10), a decoding method and a semiconductor memory. The decoding circuit (10) comprises a decoding module (11) and a register module (12). The decoding module (11) is configured to perform decoding processing on an initial counting signal, so as to obtain a target counting signal, wherein the target counting signal has a corresponding relationship with a pre-set count range, the target counting signal is a binary number comprising N bits of target signals, the N bits of target signals comprise a single-bit target signal the level value of which is a first value and (N-1) bits of target signals the level value of which is a second value, and N is an integer greater than 0. The register module (12) comprises N storage bits, and is used for correspondingly storing into the N storage bits the N bits of target signals.
Inventors:
HUANG ZEQUN (CN)
SUN KAI (CN)
SUN KAI (CN)
Application Number:
PCT/CN2022/124070
Publication Date:
March 28, 2024
Filing Date:
October 09, 2022
Export Citation:
Assignee:
CXMT CORP (CN)
International Classes:
G11C11/4063; G11C11/406; G11C29/38; G11C29/44
Foreign References:
| CN112384981A | 2021-02-19 | |||
| CN109935272A | 2019-06-25 | |||
| CN108630277A | 2018-10-09 | |||
| CN114664368A | 2022-06-24 | |||
| US20210142860A1 | 2021-05-13 |
Attorney, Agent or Firm:
CHINA PAT INTELLECTUAL PROPERTY OFFICE (CN)
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