Title:
DECODING DEVICE, CONTROL CIRCUIT, STORAGE MEDIUM, AND CHECK MATRIX GENERATION METHOD
Document Type and Number:
WIPO Patent Application WO/2024/004047
Kind Code:
A1
Abstract:
This decoding device (320) comprises: a storage unit (331) that is capable of division into PxP submatrix blocks, where P is a positive integer, and that stores a first check matrix of a maximum coding rate assumed for the check matrix of a low density parity check code used in communication; and a generation unit (332) that generates a first row obtained by replacing a portion of blocks with a 0 matrix using a unit of rows included in the first check matrix that include a submatrix in the column direction, and that further generates one or more second rows obtained by, while replacing the stipulated blocks with the 0 matrix, shifting a position of a 1 included in a submatrix of another block by a stipulated fixed value, and generates a second check matrix of a lower coding rate than the first check matrix.
Inventors:
NAKAMURA TAKAHIKO (JP)
Application Number:
PCT/JP2022/025822
Publication Date:
January 04, 2024
Filing Date:
June 28, 2022
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H03M13/19
Domestic Patent References:
| WO2019229846A1 | 2019-12-05 | |||
| WO2009004773A1 | 2009-01-08 |
Other References:
YOSHIAKI KONISHI, HIDEO YOSHIDA, TAKAHIKO NAKAMURA, KENJI ISHII, TAKAFUMI FUJIMORI: "High-speed low-power forward error correction coding technology for communications", IEICE TECHNICAL REPORT, PN, IEICE, JP, vol. 120, no. 137 (PN2020-18), 1 January 2020 (2020-01-01), JP, pages 31 - 38, XP009551646
NOKIA, ALCATEL-LUCENT SHANGHAI BELL: "LDPC design for eMBB", 3GPP TSG RAN WG1 #89, R1-1708829, 6 May 2017 (2017-05-06), XP051262697
NOKIA, ALCATEL-LUCENT SHANGHAI BELL: "LDPC design for eMBB", 3GPP TSG RAN WG1 #89, R1-1708829, 6 May 2017 (2017-05-06), XP051262697
Attorney, Agent or Firm:
TAKAMURA, Jun (JP)
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