DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD

Title:

DELAY CALIBRATION CIRCUIT, MEMORY, AND CLOCK SIGNAL CALIBRATION METHOD

Document Type and Number:

WIPO Patent Application WO/2023/011419

Kind Code:

A1

Abstract:

A delay calibration circuit, a memory, and a clock signal calibration method. The delay calibration circuit comprises: a frequency division clock generation circuit (110), configured to receive an external clock signal of a calibration input, and divide the external clock signal into four paths of frequency division clock signals on the basis of an output of the external clock signal; a calibration circuit (120), connected to the frequency division clock generation circuit (110), and configured to adjust a delay of at least two paths of frequency division clock signals in the four paths of frequency division clock signals on the basis of an adjustment signal, and output adjusted frequency division clock signals; and a detection circuit (130), connected to the calibration circuit (120), and configured to detect a pulse width of the at least two paths of frequency division clock signals, and generate the adjustment signal on the basis of the pulse width. The influence of an original low-quality external clock signal on the pulse width of the frequency division clock signals is reduced, and the read-write frequency of the memory is improved, so that the memory can perform a high-speed data read-write operation under the trigger of more stable frequency division clock signals.

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Inventors:

JIA XUERONG (CN)
WANG SONG (CN)

Application Number:

PCT/CN2022/109478

Publication Date:

February 09, 2023

Filing Date:

August 01, 2022

Export Citation:

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Assignee:

XIAN UNIIC SEMICONDUCTORS CO LTD (CN)

International Classes:

G11C11/4076; G11C11/409; H03K7/08

Foreign References:

CN112787634A	2021-05-11
CN110581701A	2019-12-17
CN101826860A	2010-09-08
CN112655151A	2021-04-13
CN110266294A	2019-09-20

Attorney, Agent or Firm:

CHINA WISPRO INTELLECTUAL PROPERTY LLP. (CN)

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