Title:
DELAY-LOCKED LOOP, DELAY-LOCKED LOOP CONTROL METHOD, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/134034
Kind Code:
A1
Abstract:
The present disclosure relates to the technical field of integrated circuits, and provides a delay-locked loop, a delay-locked loop control method, and an electronic device. The delay-locked loop comprises: a sub-path (100), which is used to perform frequency division on an input clock signal (CLK input) to generate a frequency-divided clock signal (CLK Div), wherein during a delay-locked loop locking process, the frequency-divided clock signal having a first frequency is adjusted to obtain an output clock signal (CLK output), and when the delay-locked loop is locked in a standby state, the frequency-divided clock signal (CLK Div) is adjusted to have a second frequency, the second frequency being lower than the first frequency; and a main path (200) which, when a target instruction is obtained, is used to output an output clock replica signal (DLL output) having a same phase as the output clock signal (CLK output) so that the power consumption of the delay-locked loop can be reduced.
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Inventors:
GU YINCHUAN (CN)
Application Number:
PCT/CN2022/085078
Publication Date:
July 20, 2023
Filing Date:
April 02, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H03L7/18; H03L7/081
Foreign References:
| EP0766404A2 | 1997-04-02 | |||
| CN110474633A | 2019-11-19 | |||
| CN102931979A | 2013-02-13 | |||
| US6104251A | 2000-08-15 |
Attorney, Agent or Firm:
BEIJING INTELLEGAL INTELLECTUAL PROPERTY AGENT LTD. (CN)
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