This invention relates generally to demand meter¬ ing systems and more particularly to electronically controlled time of day demand metering systems for registering the amount of electrical energy consumed during specified demand time intervals of the day.

Utility companies have generally sold electrical energy on the basis of a fixed rate schedule regardless of whether high or low demand-has been made upon the electrical generation system. This type of rate sched- uling has not provided the consumer with the incentive to voluntarily reduce his power consumption, particu¬ larly during those periods of high peak demand. As a result, in order to prevent overloading the power dis¬ tribution system, utility companies have had to add additional power generating capacity which can be brought on line during peak demand periods. The addition of this power generating capacity has created an unnecessary burden.

In order to reduce peak power system demand, and in recognition of the higher cost of producing peak demand power, multiple rate metering of electrical power consumption has been proposed. Thus, electrical energy consumed duringso-called "on-peak" periods is to be billed at a higher rate than energy consumed during so-called "off-peak" periods.

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One previously proposed multiple rate metering sys tem is disclosed in U.S. Patent 4,050,020 Germer et al (hereinafter referred to as Germer I) . That system is an electronic time-of-day metering system which is pre- programmed to selectively activate two sets of register dials dials at predetermined times of the day to regist the amount of power consumption during designated peak intervals (e.g. high-peak and mid-peak). The present invention is ideally suited for operation with the system of Germer I. U.S. Patent 4,093,997 entitled

"Portable Programmer for Time-of-Day.Metering Register System" (hereinafter referred to as Germer II) dis¬ closes a programmer for programming the meter of Germer I and is useful also for programming and controlling the system of the present invention. The disclosures o Germer I and Germer II are hereby incorporated in the present description.

To further encourage consumers to utilize less pow during on-peak periods, "demand" metering has been sug- ges ed, with an extra charge to each metered consumer based on the maximum demand for power by that consumer during any one demand sampling interval (referred to hereinafter as "demand intervals") during the billing period. The demand intervals are uniform time periods which may typically be 15 minutes in length. A prior maximum demand meter is disclosed in U.S. Patent 3/913,014 Halstead et al. The demand metering is pref¬ erably carried out only during peak demand periods to encourage Consumers to schedule heavy loads for off- peak periods.

The demand metering may be advantageously combined with a two level time-of-day metering system to provide a three rate billing structure. Typically, in prior systems, a separate meter has been provided for the demand metering function.

It is an important object of the present invention to provide an improved demand metering system which is very easily integrated with a single or multiple rate watt-hour metering system in a single meter structure. In carrying out the invention there is provided a demand metering system for registering the maximum demand for electrical energy during successive demand intervals comprising means for continuously measuring the rate at which electrical energy is transmitted through said metering system, a first resettable means connected to said measuring means for storing a measure¬ ment indicative of the amount of electrical energy transmitted through said metering system during each demand interval of successive demand intervals of equal duration, timing means operable to determine the dura¬ tion of said demand intervals and connected to reset said- first resettable means at the end of each demand interval, a second resettable means for storing a mea¬ surement indicative of maximum demand in terms of the maximum amount of electrical energy transmitted through said system ^' during any one of said demand intervals and for retaining and increasing the measurement upon the achievement of any greater electrical energy transmis¬ sion during any subsequent demand interval to continu- ously update the maximum demand measurement until said second resettable means is reset, wherein said means for measuring the rate at which electrical energy transmit¬ ted through said metering system comprises means for generating .pulses having a repetition frequency propor- tional to the rate at which electrical energy is trans¬ mitted through said system, said first resettable means comprises a first digital counter connected to receive and count the pulses from said pulse generating means, said timing means comprises an electrical circuit for periodically providing reset signals to said first

digital counter to thereby determine the duration of each demand interval by ending the current demand interval and starting a new demand interval, said secon resettable means comprises a second digital counter connected to receive said electrical energy rate oulses from said pulse generating means, enabling means for said second counter comprising a comparison means connected to both of said counters and operable to compare the counts stored in said counter and to provide a compare signal when the counts are equal, and said enabling means further including means for detect¬ ing the concurrence of said comparison signal and the continuation of the demand interval for issuing a demand addition signal connected to enable said second counter to count said pulses from said pulse generating means until the end of- the demand interval so that said second counter stores a number indicative of the maximum energy demand during any demand interval.

In the accompanying drawings: FIG. 11s a schematic block diagram of a demand metering system in accordance with the present inven¬ tion.

FIG. 2 is a front view of a preferred form of meter incorporating the present invention. FIG. 3 is a schematic block diagram of the demand logic circuit of FIG. 1 and illustrates its intercon¬ nection to the programmable control circuit.

FIG. 4 shows how FIGS. 4A and 4B should be combined FIGS. 4A and 4B show a detailed schematic logic diagram of a preferred system embodiment of FIG. 3.

Referring first to FIG. 2, two sets of decade gear driven register dials 13 designated "A" (the on-peak register) and 17 designated "Demand" (for registering demand interval power consumption) are included in the mechanical portion of the meter as illustrated. These two sets of dials are positioned above and below a conventional set 19 of five dials which continuously register total kilowatt-hour consumption in the same manner as a conventional five-dial pointer register. Either set if dials 13 or 17 can be engaged or dis¬ engaged as determined by the programmable control cir¬ cuit and the Demand logic circuit of FIG. 1. When disengaged, the dials 13 and 17 remain fixed at their last reading until again engaged. _ _t The purpose of having the 13 and 17 dials selective¬ ly engageable is to provide the utility company with the basis for a three-level rate billing structure including total power usage on the Total register 19, ON-peak power usage on the A register 13, and maximum power demand on the Demand Register 17.

Referring to FIG. -1, the system preferably includes a Programmable Control Circuit 11, the details of which are disclosed in Germer I. Control Circuit 11 generates control signals at programmed times for selectively engaging the Peak Register 13 and for enabling a Demand logic Circuit 15 to provide a demand register engagement signal to the Demand Register 17. The Total Register 19 receives no control signals and is driven in a conven¬ tional manner as is common in the standard kilowatt hour meter.

Control Circuit 11 is energized from a 60 Hz power line via a power supply 21. A Battery Charger 23 re¬ ceives current from the Power Supply 21 to charge a Rechargeable Battery 25. The Battery 25 is utilized to provide current to the control Circuit 11, both direct-

ly and through a DC-DC Converter 27, to keep the timing function of the control circuit operable during a power outage. The 60 Hz input is also used as a time base fo control circuit 11 and for the Demand Logic Circuit 15. A Quartz Crystal Oscillator 29 is also provided, and serves as an alternate time base input to the control circuit during power outages.

The Control Circuit 11 also includes a timer in th form of a 7-day clock which performs the timing functio for enabling the Demand Logic Circuit 15 and for engagi and disengaging the Peak Register 13. The output of th 7-day clock is resolved into 15-minute intervals, with each output capable of controlling one or more timed functions at any one of the 15-minute intervals. As an example, signals from the 7-day clock can control dis¬ engagement of the Peak Register 13, enablement of the Demand Logic Circuit 15 and, if desired, switch on or o a Load Control Circuit 31 to control a customer's switc not shown. The Control Circuit 11 can be programmed to enable or inhibit the operation of any one or all of th Demand Logic Circuit 15, the Load Control Circuit 31 or the Peak Register 13 at any time of the day on a 7-da . basis. The timer also drives a- digital Time Display 33 which sequentially displays the day, hours and minutes (see FIG. 2) .

The Control Circuit 11 is electronically programme by means of a Portable Programmer Tester 35 which is preferably carried out as disclosed in Germer II. The Portable Programmer Tester 35 is connected to the Contr Circuit 11 by an electrical connector 37 (FIG. 2) which is accessed through a sealable opening in the meter enclosure (not shown) . The Programmer Tester contains its own battery operated power supply, an oscillator controlled 7-day clock and appropriate circuitry for testing, reprogramming and setting the time of day

demand metering system of the present invention.

Still referring to FIG. 1, the Demand Logic Circuit 15 receives input signals from a pulse initiator circuit 39 and a manually operable Monthly Reset Switch 41. The Pulse Initiator 39 continuously provides pulses to the Demand Logic Circuit 15 at a frequency proportional to the rate of electrical energy transmission through the system. Reset Switch 41 is accessed through the meter front cover (see FIG. 2) and provides a reset signal to the Demand Logic Circuit 15 when actuated by a utility company employee such as a meter reader. The Reset Switch 41 is normally utilized to reset the Demand Logic Circuit 15 each month after the meter dials have been read. ^■ * FIG. 3 which is a schematic block diagram of the Demand Logic Circuit 15 of FIG. 1. The Programmable Control Circuit 11, the pulse initiator circuit 39, and the reset switch 41, are re-illustrated in FIG. 3 to show their relationship with the various circuits of the Demand Logic Circuit 15.

Control Circuit 11 receives the 60 Hz power supply voltage wave which it utilizes as a time base to gener¬ ate an output control signal as ^' a group of pulses desig¬ nated PI on a conductor 43 at 15 minute intervals. Through its program and clock circuits, the Control Circuit 11 is operable to supply the Pi signal at specific intervals to be either in or out of phase with the 60 Hz signal as available in the Demand Logic Circuit 15 ^' . "In phase" enables the Demand Logic Circuit 15 and "out of phase" disables that circuit.

The Demand Logic Circuit 15, as shown in FIG. 3, consists of Time Interval Counter/Logic 49, Demand Enable On/Off Peak Detector Logic 51, Sequencing Logic 53, Demand Interval Counter/Logic 55, and the Solenoid and Clutch Drive 47. The.Pulse Initiator Logic 39 and

the Manual Reset switch 41, mentioned in connection wit FIG. 1, are again shown.

The PI control pulse signal supplied at predeter¬ mined intervals (e.g. 15 minute intervals) from Control Circuit 11 is supplied to each of the logic circuits 49, 51 and 53.

The demand metering system in accordance with the present invention as described below in connection with FIG. 3 and succeeding figures is preferably, though not necessarily, combined in a watt-hour meter which also separately registers total kilowatt hours consumed, and kilowatt hours consumed during a peak demand period. The maximum demand may be measured during demand interv occurring throughout the 24 hour day. However, the maximum demand is preferably measured only during peak demand times of day. Typically, maximum demand may be measured throughout the entire peak load period during which peak load kilowatt hours are measured. However, the time of day during which maximum demand is measured need not necessarily coincide exactly with the period during which peak demand kilowatt hours are registered. In the following description and discussion of the demand metering system, reference is made to on-peak an off-peak intervals and detectors. It should be under- stood that these terms are used in connection with the description of the demand metering system to designate the time period when demand metering is being carried out as "on-peak" and when demand metering is not being carried out as "off-peak", and those terms are used in this connection without reference to whether or not the on-peak and off-peak periods correspond to the time of day during which so-called on-peak kilowatt hours are metered. Furthermore, in the detailed description of the demand system, so-called off-peak signals are refer red to in an even more specialized sense as signals

which may signify the end of a demand interval, as well as the end of the entire on-peak demand metering time period. These uses of the terms "on-peak" and "off-peak" are thus to be distinguished from the use of those terms in connection with "on-peak" kilowatt hour metering.

Referring again to FIG. 3, the programmable control circuit 11 not only provides the signals necessary for determining the end of one demand interval and the begin¬ ning of the next demand interval, but also provides signal information indicating whether or not it is the time of day during which demand metering is to be carried out. In the preferred embodiment, the timing signals are supplied from the programmable control circuit on connec¬ tion 43 as a series of four pulses PI occurring every fifteen minutes, with the pulses occurring in phase with the 60 Hz waveform when demand metering is to be carried out (on-peak) , and out of phase with the 60 Hz power signal when demand metering is not to .be carried out (off-peak). As long as an off-peak condition exists, the detector logic circuit 51 detects that condition and provides an off-peak signal (OFPK) to the demand interval logic (55) .

The demand interval logic 55 includes an OR gate 61, a first digital counter 63 referred to as a present interval counter, a second, digital counter 65 referred to as a maximum count per interval counter, and a com¬ parison circuit 67. Circuit 67 is connected to both counters 63 and 65 for determining when the counts in the two counters are equal and then operable to provide a signal designated "A = B" on connection 69 to the de¬ tector logic circuit 51. Each counter has a count pulse input connection C connected to receive the energy rate . pulses PS from the pulse initiator logic 39. Each counter 63, 65, also includes an enable input E, which must receive an enabling signal in order to register the

count, and a reset input R upon whi _. ch a signal is . effective to reset the counter,

Counter 63 is continuously supplied with an enable signal E as indicated in the drawing. Counter 63 is supplied with a reset signal through OR gate 61 derive from the off-peak signal (OFPK) from detector logic 51 during off-peak intervals, or at the end of a demand period. Whenever counter 63 receives a reset signal, it is reset, and remains reset, and does not count up as long as the reset signal continues. Accordingly, a long as an off-peak signal continues, the counter 63 does not count. The counter 65 has its reset terminal connected to receive only the manual reset signal (MR) from the manual reset switch 41 which is normally actuated by the meter reader at the time the meter is "read, generally once a month. The manual reset signal (MR) is also effective through OR gate 61 to reset counter 63.

When on-peak conditions exist, the detector logic circuit 51 operates to remove the off-peak signal (OFP from the input to OR circuit 61, permitting the presen interval counter 63 to commence counting the pulses received from the pulse initiator logic 39. At the en of the demand interval (typically fifteen minutes) the detector logic circuit 51 and the time interval counte logic 49 operate in response to the time interval sign Pi from the programmable control circuit 11 to provide an end-of-interval signal in the form of a pulse (OFPK) to OR gate 61 to reset the present interval counter 63. This operation is repeated again and again for every demand interval during the on-peak period of the day. If, during any demand interval, the count in the counter 63 reaches a value equal to the count previous stored in the maximum count per interval counter 65, a determined by the compare circuit 67, the compare

circuit 67 issues a comparison signal "A = B" to the detector logic 51. If the demand interval is not over, and continues, then the detector logic 51 detects the concurrence of the comparison signal "A = B" and the continuation of the demand interval and operates to issue a demand addition signal (DON) . This signal is connected at connection 83 to the enable input E of the counter 65 to enable that counter to count in tan¬ dem with counter 63 in response to the pulses from pulse source 39. At the end of that demand interval, the enabling signal DON is discontinued to stop the counter 65 concurrently with the stopping of the counter 63 by the signal OFPK received through OR gate 61 at the reset input R of counter 63. . - Thus, the count stored in counter 65 is increased whenever necessary to equal the highest count ever counted and stored in present interval 'counter 63.. In this manner, counter 65. is caused to count and retain storage of a maximum count from any demand interval until the counter is next reset.

When the demand addition signal DON is available, it is also supplied at connection 81 to a sequencing logic circuit 53 which provides a DEM signal on connection 45 to a meter register solenoid and clutch drive 47 to engage the demand register 17 (previously described in connection with FIG. 2) for providing a visible read¬ out of the demand figure. That demand figure is pro¬ portional to the maximum count stored in counter 65. The time interval counter logic 49 may be programmed to select different demand intervals. In the preferred form, the demand interval counter logic consists essen¬ tially of a digital counter which provides an end-of- interval signal "EOI" at the end of one fifteen minute period, two fifteen minute periods (30 minutes) , or after a longer interval which is a higher multiple of

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the basic fifteen minute timing periods as received from the programmable control circuit 11.

The pulse initiator logic 39 issues pulses at a frequency proportional to the rate of energy transmis- sion through the system, and may be carried out by a simple photoelectric detector which responds to light pulses transmitted through one or more holes in the watt-hour meter eddy current disc, as described more fully below. For a more detailed description of the operation of the invention reference is now made to FIGS. 4,- 4A and 4B. FIGS. 4A and 4B should be arranged together as shown by FIG. 4. FIGS, 4A and 4B are sometimes refer¬ red to jointly below as FIG. 4. FIG. 4 illustrates details of the components, circuits, and connections o FIG. 3. Detector logic circuit 51 includes a demand enable DEN flip-flop 68 connected to receive 60 Hz power as one input and PI signals inverted through an inverter 119 as another input. During an off-peak pow period, flip-flop 68 is in the reset state generating binary 0 and 1 output signals DEN and DEN respectively Under off-peak conditions, the PI signal 'consists of four pulses every fifteen minutes which are out of phase with the 60 Hz power pulses. This combination of inputs to the DEN flip-flop 68 caused that flip-flo to reset on the trailing edge of the first PI pulse.

The resultant binary 1 DEN signal is applied to an OR gate 57 causing it to generate a binary 1 OFPK signal. This latter signal is applied via a conductor 59 to an OR gate 61 in the Demand Counter Logic 55 of FIG. 4B. The OFPK signal enables OR gate 61 to apply a binary 1 MR1 reset signal to the R terminal of Present Interval counter 63, thus keeping that counter reset.

When the meter reader activates the MR switch 41 an MR signal is applied to an R (reset) terminal of Maxim

Count per Interval Counter 65, thus resetting that counter. As soon as Counter ^' 65 is reset, the contents of both Counters 63 and 65 are detected as being equal by a Comparator 67 receiving the counter outputs at its two sets of input terminals. The comparator then provides a binary 1 "A = B" signal on Conductor 69 to an AND gate 71 of FIG. 4A. AND gate 71 is then enabled whenever the DEN signal from flip-flop 68 (the only other input) later goes to a binary 1 during an on-peak period.

The binary 1 OFPK signal on Conductor 59 keeps a "demand on" flip-flop 70 (DON flip-flop) in the reset state and also keeps an Interval Counter 73 reset via two NAND gates 75 and 77. Resetting the i terval Counter 73 effectuates the generation of a binary 0 End of Interval Signal EOI on a Conductor 79. The EOI Signal is applied as -a second input to OR gate 57, and its purpose will subsequently be described. At this time the DON Signal on conductors 81 and 83 is a binary 0, since the flip-flop 70 is reset. Thus Counter 65 does not count the PS pulses because the application of a binary 0 Signal at its enable (E) input terminal does not enable the counter. •

The Pulse Initiator Logic 39 of FIG.l and FIG. 2 is illustrated in detail in the lower left corner of FIG. 4B. The purpose of the Pulse Initiator Logic is to continuously provide sync pulses PS at the Q output of a flip-flop 95 during meter operation. The repetition rate of these pulses is directly proportional to the amount of power being transmitted through the metering system. The Pulse Initiator 39 is comprised of a pair of light emitting diodes 85 and 87 connected- in series between a voltage potential +V and ground via a load resistor 89. During meter operation, diodes 85 and 87 continuously produce light which impinges on rotating

watt meter eddy current rotor disc 91 mounted in the time of day demand meter (FIG. 2) . Disc 91 has been fabricated to contain one or more apertures 93 throug which the light from the respective diodes 85 and 87 can pass as the disc aperture rotates past those diod A pair of photo transistors PT1 and PT2 are juxta- positionally aligned with the disc aperture so that t light from the diodes 85 and 87 impinges on the base of their respectively associated transistors as the rotating disc comes into alignment with the respectiv diodes and transistors. Photo transistors PTl and PT are of the NPN type having their emitters connected in common to ground so that each transistor will cond to generate a logic 0 signal at its collector as ligh strikes the base. Each transistor output is applied to a Pulse Sync flip-flop 95 via an associated one of inverters 97 and 99. Flip-flop 95 is triggered to alternately set and reset by the binary 1 signals from the two inverters as their respectively associated transistors are caus to conduct by the light through the meter disc apertu 93. The output of the Pulse Sync flip-flop 95 is an alternating sync Pulse PS having a repetition frequen which is proportional to the amount of power being transmitted through the system. The PS Pulses are continuously applied to a C or clock input terminal o each of the Counters 63 and 65.

During "on-peak" operation of the demand metering system, the PI signals are in the form of four pulses every fifteen minutes which are in phase with the 60 Hz power pulses- and this in phase relationship causes the DEN flip-flop 68 to set, activating the counting of the counter 63, as described more fully below.

When the MR switch 41 is actuated, it resets both counters 63 and 65, causing the "A=B" signal to go to

a binary 1. At the time of reset, if the DEN flip- flop 68 is set (ON-peak) , AND gate 71 is enabled to set the DON flip-flop 70. Both of the counters 63 and 65 will then begin counting the PS pulses in unison, thus keeping the A=B signal at a binary 1. Counters 63 and .65 will continue to count the PS Pulses until the Control Circuit 11 generates a PI signal. This latter PI signal will either reset the DEN flip-flop 68 to enable OR gate 57 (system goes to off-peak) or have no affect at all on that flip-flop (system stays on-peak) . The PI signal also causes an Interval Pulse flip-flop 101 to set. When flip-flop 101 sets, a 15 minute signal 15 MP is applied to counter 73 causing it to generate the EOI (end of interval) signal on connection 79 which also enables OR gate 57.

When OR gate 57 is enabled by either the DEN or EOI signals. Counter 63 and the DON flip-flop 70 are both reset by the OFPK signal. With Counter 63 reset, it is conditioned to begin counting from zero at the start of the next demand interval. Since the DON flip-flop 70 is now reset, the DON signal is a binary 0, disabling Counter 65 from counting the PS Pulses. The A=B signal is now a binary 0 to prevent the DON flip-flop 70 from again setting until the contents of counters 63 and 65 are again equal.

At the termination of the first demand interval following system reset," Counter 65 contains a count proportional to the amount of energy transmitted through the system during the first demand interval. At the start of a second demand interval, the DEN flip-flop 68 is set, and ^" OR gate 57 is disabled to ^• cause the OFPK signal to go to a binary 0. The M_R1 signal from OR gate 61 then goes to a binary 0 and the Present Interval Counter 63 begins to count the PS Pulses. The A=B output of the Comparator 67 will re-

main at a binary 0 so long as the contents of Counter 63 are less than the previously accumulated count in Counter 65.

If the demand for energy in the present interval exceeds the maximum in the previous maximum demand interval as manifested by the contents of Counter 65, the contents of Counters 63 and 65 become equal, thus causing the A=B signal to go to a binary 1. Since th DEN flip-flop 68 is set, AND gate 71 is now enabled t set DON flip-flop 70. The DON signal on connection 8 now goes to a binary 1 to enable Counter 65 to begin counting in unison with Counter 63. Also at this tim the Demand Register 17 is engaged to accumulate a registration of the additional amount of energy being transmitted during the present demand interval.

Counters 63 and 65 will continue to count and the Demand Register will remain engaged until the DON fli flop 70 is reset as previously described.-

The following description pertains to the sequenci logic 53. In FIG, 4A there is shown a sequence flip- flop 72 (SEQ flip-flop) receiving a +V binary 1 enabl input at its D (set) input terminal ^" and providing as output an SEQ signal at its Q- output terminal. The D signal, applied to the C terminal of the SEQ flip-flo 72 when it goes to a binary 1 (when maximum counter 6 is enabled) causes the SEQ flip-flop to set, driving the SEQ signal to a binary 0. The SEQ signal is appl as one input to an OR gate 103, with the other input being the Pi Control signal. Since the Pi signal is always a binary 0, except at the end of a 15 minute interval, OR gate 103 is now disabled. This disable¬ ment causes the OR gate 103 output signal R-CTR to go to a binary 0 state.

The R-CTR signal is applied to a reset (R) control terminal of a Sequence Counter 105 of the Sequencing

Logic 53. Counter 105 operates to remain in the reset state so long as the R-CTR signal is a binary 1 (i.e. it cannot count) . However, as soon as the R-CTR signal goes to a binary 0, counter 105 is enabled to count the 60 Hz Pulses from the power supply 21 (FIG. 1) applied to its C (clock) input terminal. The Sequence Counter 105 operates as a conventional five bit binary counter which is triggered on the rising edge of the 60 Hz pulses to sequentially generate output signals Q2 - Q5, with Ql being shown but not used.

An Exclusive OR gate 107 receives the 60 Hz and DON signals to generate a first strobe output signal ST1. As is well known in the art, an exclusive OR gate gener¬ ates a binary 0 output when its inputs ar^e equal and generates a binary 1 output only when its inputs are opposite. Therefore, ^' the ST1 signal is a 60 Hz square wave which is 180 degrees out of phase with the 60 Hz pulses.

The ST1 signal is applied simultaneously to an inverter input of each of two delay one shot multivibra¬ tors (ST2 OS) 109 and (ST3 OS) 111. Each of these delay circuits is triggered on the falling edge of the ST1 signal to generate respective second and third output strobe signals ST2 and ST3. Since the ST2 sig- nal is taken from the 1 output terminal of ST2 OS and the ST3 signal is taken from the 0 output terminal of ST3 OS, these signals are 180 degrees out of phase with respect to each other. The pulse width of the ST3 signal is approximately one-half the pulse width of the ST2 signal.

Referring back to Sequence Counter 105, two of that counter's output signals, Q3 and Q4, are applied to an AND gate 113, which is enabled when those two signals each achieve a binary 1 state (upon the achievement of an advanced binary count . The output of AND gate 113

is applied to a NAND gate 115 in conjunction with the ST2 signal from circuit 109 to generate a fourth strob signal ST4. In the operation of a NAND gate, its output goes to a binary 1 only when its inputs are opposite or both binary O's and provides a binary 0 output when its inputs are -all binary l's. The opera¬ tion of NAND gate 115 is a series of negative going pulses having the.same pulse width as the ST2 signal and which occur each time the ST2 signal and the outpu of AND gate 113 are both binary l's.

A Demand flip-flop 116 (DEM flip-flop) receives the ST4 signal at its reset (R) terminal and the ST3 signa at its set (S) input terminal. The DEM flip-flop 116 is triggered to set and reset on the rising edge of th ST3. and ST4 pulses respectively to generate a positive going Demand output pulse DEM having a pulse width approximately half the pulse width of the ST4 pulse.

The DEM pulse is applied to a Clutch Solenoid Drive (Triac) 117 of the Meter Register Solenoid and Clutch Drive 47. The Solenoid Drive Circuit 117 is comprised of the aforementioned transistor 73 and triac 69 of Germer I,

The output of the Solenoi 'Drive 117 is a Clutch Drive Signal similar in characteristics to the DEM signal and is utilized to drive the Clutch and Solenoi Coil 59 of Germer I. The 60 Hz pulses are also applie to the Solenoid Coil 59.

When the Clutch Drive (DEM) signal is in phase with the system 60 Hz signal from power supply 21, the clut is engaged to drive the Demand Register dials 17 and thus record the amount of power being consumed during the present demand interval.

When the Q5 stage of Counter 105 is set a binary 1 (Q5) pulse is applied to a reset (R) terminal of the SEQ flip-flop causing the SEQ signal to now go to a

binary 1. The SEQ signal now enables OR gate 103 allow¬ ing the R-CTR signal to reset counter 105. Counter 105 will remain reset until the SEQ flip-flop is again set. Earlier the INTVL Pulse flip-flop 101 of FIG. 4B is reset by the Q2 pulse applied to the R input terminal of that flip-flop. Flip-flop 101 is reset in prepara¬ tion to generate the 15 MP signal for the Interval Counter upon receipt of the next PI signal during either, (1) an end of demand interval while on-peak, (2) when the system is directed to off-peak by the PI signal, or (3) when the system is directed to on-peak after monthly reset. The Q2 signal is also applied to NAND-gate 75, however, it has no further effect on the system at this time. . ^~ Under "on-peak" conditions, the PI signal is a series of four pulses each occurring in phase with the 60 Hz pulses ^' from power supply 21. The DEN flip-flop 68 is set by the in phase PI and 60 Hz signals to command the Logic Circuit 15 to go on-peak, on Demand Register 17. The PI signal is applied to an Inverter 119 and inverted to a PΪ signal at the clock (C) input of the DEN flip-flop 68. The 60 Hz signal is applied simul¬ taneously to the set/reset D input of the DEN flip- flop 68. The DEN flip-flop 68 is triggered on the positive edge of its C input on the trailing edge of the PI signal when it goes negative to apply a binary 13?T signal to the DEN flip-flop 68 causing it to set in response to the binary 1 60 Hz pulse present at the D input. ' r The PI signal is also applied to the set (S) input terminal of the INTVL. PULSE flip-flop 101, causing that flip-flop to set, generating the 15 MP signal. The 15 MP signal has no effect on the Interval Counter 73 at this time, because it can be triggered only on the rising edge of the 15 MP pulse, which, in this

instance, occurs prior to the DEN signal going to a binary 1. As such, the output of NAND-gate 77 goes to a binary 0 after the 15 MP signal and Counter 73 is unaffected by the L5 MP signal.

Referring back to FIG. 4A, the Pi signal is also applied to a set (S) input terminal of the SEQ flip- flop 72 via an OR gate 125 causing that flip-flop to se making the SEQ signal go to a binary 0. The SEQ signal is applied to one input of OR gate 103, thus removing the constant R-CTR binary 1 reset signal from the Sequence Counter 105. The OR gate 103 is now enabled to allow the Pi signal to control the reset operation of Counter 105. The Ql stage of Counter 105 is set on the rising or leading edge of the 60 Hz signa applied to the C input of that Counter and then immed¬ iately reset by the rising edge of the R-CTR signal resulting from the PI signal passing through OR gate 10 Counter 105 is set and reset three times in response to the three R-CTR signals (PI passing through OR gate 103 After the last R-CTR pulse (also last PI pulse) has been generated, OR-gate 103 is disabled to now allow Counter 105 to count up as previously described above.

The ST1-ST4 signals are generated in the manner previously described, and the DEM signal is generated t engage the Demand Register 17 in the same manner as previously described.

In the present invention, it is desirable to progra the Time Interval Counter/Logic 49 to generate an ΞOI signal every fifteen minutes. However, this is not a limitation of this circuit. It can also be programmed to generate the EOI signal at other intervals (eg. ever 30, 60, 120, etc. minute intervals) .

On the jumper pin connector outputs of Counter 73, can be seen that if the jumper 123 is connected to the 15 minute output (as shown) , one EOI signal will be gen

\

ated for each 15 MP pulse, thus providing 15 minute Demand intervals. If a 60 minute Demand interval is desired, jumper 123 is moved to the 60 minute (Q3) out¬ put and the Counter 73 will have to count four 15 MP pulses in order to generate one EOI output signal. Thus, for one PI signal every fifteen minutes, it would take one hour for the Counter 73 to generate the EOI signal to terminate the present demand interval. The EOI signal enables -OR gate 57 to generate a binary 1 OFPK signal resetting the DON flip-flop 70.

The OFPK signal enables OR gate 61 to apply a binary 1 MRl reset signal to the Present Interval Counter 63. The MRl signal resets counter 63, having the effect of causing the A=B signal to go to a binary 0^ if the counters 63 and 65 were equal and counting together. This is due to the fact that the contents of Counters 63 and 65 are no longer equal.

AND gate 71 of FIG. 4A is then disabled by the A=B binary 0 signal, and at the same time the EOI signal resets the DON flip-flop 70 via OR gate 57. The resulting binary 0 DON signal on Conductor 83 now dis¬ ables Counter 65 from counting the PS pulses until again enabled at the next demand interval.

The Q1-Q5 and ST1-ST4 signals are generated in the same manner as previously described, with the exception that the ST1 signal is now out of phase with the 60 Hz signal. This is due to the fact that the DON signal at the input to the Exclusive OR gate 107 is a binary 0, thus'-reversing the polarity of operation of that gate. It is this out of phase relationship of the ST1 and 60 Hz signals which causes the clutch solenoid 59 of Demand Register 17 to be disengaged.

Earlier in the operation of sequence counter 105, the Q2 binary 1 output signal in conjunction with the binary 1 OFPK signal (EOI is a binary 1) enables NAND

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gate 75 to apply a binary 0 signal to NAND gate 77, wh in turn applies a binary 1 reset signal to Counter 73, thus terminating the EOI signal. The Q2 signal also resets the INTVL.PULSE flip-flop 101 at the same time, terminating the 15 MP signal.

The invention also includes means for inhibiting operation of the Demand metering system in the event of a power failure. Referring to FIG. 4A there is shown conventional RC Integrator Delay network 127 receiving the ST3 signal. The ST3 signal is continuously gener¬ ated so long as the 60 Hz signal is present at the inp to gate 107. So long as the ST3 signal is continuousl applied to the Integrator 127, its output to a conven¬ tional squaring amplifier 129 remains at a constant negative or binary 0 potential. However, in the event of a power failure which lasts, for example, for five or more seconds, the Integrator generates an output pul to amplifier 129 similar to that shown on Conductor 131 The input Pulse to amplifier 129 is applied as a binary 1 squared off pulse to a reset R terminal of the DEN flip-flop 68 and also as a set pulse to the S input terminal of the SEQ flip-flop via OR gate 125.

Resetting the DEN flip-flop 68 takes the system out of the demand interval mode to reset the DON flip-flop 70 via OR gate 57,. while setting the SEQ flip-flop 72 disables OR gate 103 so that upon restoration of power, the sequence circuit 53 disengages the clutch in the manner as previously described.