DEMODULATOR CIRCUIT AND RECEIVER DEVICE

WIPO Patent Application WO/2004/023751

A1

A sampling block (40a-1) uses a frequency, which is obtained by multiplying the frequency of an intermediate frequency signal (RIFs) by 1/(m + 0.25) or 1/(m + 0.75) where “m” is zero or a natural number, to sample the intermediate frequency signal (RIFs), thereby producing signals of phase differences “0”, “&pgr /2”, “&pgr ” and “3&pgr /2”. A polarity adjusting block (40a-2) causes the polarity of the phase difference “&pgr ” to be coincident with the signal of phase difference “0”, while causing the polarity of the phase difference “3&pgr /2” to be coincident with the signal of phase difference “&pgr /2”. A signal combining block (40a-3) combines the signals of phase differences “0” and “&pgr ”, which have a phase difference “&pgr ” therebetween, and holds and outputs the resultant combined signal as a demodulated signal (PI). The signal combining block (40a-3) also combines the signals of phase differences “&pgr /2” and “3&pgr /2”, which have a phase difference “&pgr ” therebetween, and holds and outputs the resultant combined signal as a demodulated signal (PQ). In this way, a simple structure can be used to provide a demodulator circuit and receiver device that can easily obtain satisfactory demodulated signals.

SAIJO KAZUYUKI (JP)
JEONG MOONJAE (JP)

PCT/JP2003/010655

March 18, 2004

August 22, 2003

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SONY CORP (JP)
SAIJO KAZUYUKI (JP)
JEONG MOONJAE (JP)

H04L27/38; H03D3/00; H04L27/22; H04L27/227; (IPC1-7): H04L27/00; H04L27/22

JPH09149091A	1997-06-06
JPH04177946A	1992-06-25
JPH09130148A	1997-05-16
JPH09306194A	1997-11-28

Yamaguchi, Kunio (Hirayama Building 15-2, Uchikanda 1-chom, Chiyoda-ku Tokyo, JP)

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