Title:
DENSE VIA PITCH INTERCONNECT TO INCREASE WIRING DENSITY
Document Type and Number:
WIPO Patent Application WO/2024/088210
Kind Code:
A1
Abstract:
An enhanced integrated circuit interconnect package, method and multiple-layer integrated circuit laminate structure enable increased routing density per layer and maintains signal integrity performance. A differential signal via pair of vertical interconnect vias provide differential signaling. The vias of the differential signal via pair are positioned closely spaced together with each via offset from a center axis of an associated LGA contact, minimizing space between the differential signal vias and maintaining signal integrity performance, and providing increased available wiring signal channel.
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Inventors:
PREDA FRANCESCO (US)
CHUN SUNGJUN (US)
HEJASE JOSE A (US)
TANG JUNYAN (US)
ROY PALADHI PAVEL (US)
PHAM NAM HUU (US)
BECKER WIREN DALE (US)
DREPS DANIEL MARK (US)
CHUN SUNGJUN (US)
HEJASE JOSE A (US)
TANG JUNYAN (US)
ROY PALADHI PAVEL (US)
PHAM NAM HUU (US)
BECKER WIREN DALE (US)
DREPS DANIEL MARK (US)
Application Number:
PCT/CN2023/125903
Publication Date:
May 02, 2024
Filing Date:
October 23, 2023
Export Citation:
Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
IBM CHINA CO LTD (CN)
International Classes:
H01L23/538
Foreign References:
| US20170229407A1 | 2017-08-10 | |||
| US8119931B1 | 2012-02-21 | |||
| CN113573463A | 2021-10-29 |
Attorney, Agent or Firm:
ZHONGZI LAW OFFICE (CN)
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