Claim Of Priority Benefit

This application claims the priority benefit of commonly-assigned, co-pending U.S. provisional patent application no. 63/243,662, filed 13 September 2021, entitled “Diamond Wafer Based Electronic Vehicle Power Electronics”, Attorney Docket No. DFI-004-PROV2, and co-pending U.S. provisional patent application no. 63/233,616, entitled “Diamond Wafer Based Electronic Vehicle Power Electronics”, Attorney Docket No. DFI-004-PROV, the entire disclosures of which are incorporated herein by reference.

Background

Advancing Energy Efficiency in EV Power Electronics

The large majority of power inverters architecture consist of converting the DC voltage from the battery to a 3 -phase AC format compatible with the electric traction motor. Today power conversion ranges from 50 to 250kW (400kW peak) depending on models. Years to come will see the emergence of MW systems (trucking industry, naval transportation, and more importantly the aerial e-mobility). Each phase requires two power switches mounted in a so-called “half bridge” topology. During operation, because the three-phases are shifted at a 120-degree angle, always two switches are closed (ON) simultaneously, the other four being open (OFF).

In order to evaluate the inverter efficiency, conduction losses are calculated from the voltage difference when the switch is closed multiplied by the current flowing into the switch, of course multiplied by 6 (3 x 2 = 6 switches). The level of power losses generated is substantial, and designers always have tried to reduce it to increase driving range or battery size reduction. Some other considerations such as wire-bonds stress and capacity, gate-drivers performances and overall system size and cost are as well part of the equation when designing a power traction inverter. Eventually the rule of thumb to reduce power losses has been so far “use more silicon surface area or use a better heat sink”. Both “recommendations” have large drawbacks. The consideration of using more silicon switches indeed reduces power conduction losses since the “ON” state current is shared among a greater number of switches therefore reducing the power to be dissipated, but the switching losses increase accordingly especially with IGBTs. The drawback is the exponential surface attachment to be used, the multiplication of weak links in the power path such as wire bonds, the disparity from dies to dies, the physical distance expansion leading to detrimental parasitic inductances and the difficulty to perfectly synchronize each die to their companion die, eventually ending with an unrequired complexity and a poor efficiency for the effort deployed. Cost consideration finished to prove this doctrine wrong.

Cooling strategy on the other hand has been an interest of experiments and R&D studies for many years. Rather than only focusing on silicon improvements, designers had a second sense that reducing operating temperature of the dies could be the path to power efficiency, cost reduction and greater reliability. Though that intuition is certainly correct, nowadays available materials to ensure a satisfying result is by far unreachable.

Because the electrical and thermal paths for power silicon are identical and both of substantial magnitude, it is extremely challenging to literally disconnect them to direct the thermal path to a liquid coolant that needs to be electrically isolated for safety reasons and the electrical path that needs to be as short and resilient as possible. That disconnection mechanism (the “dielectric”) is accomplished through techniques and technologies illustrated in Figures 1 A-1C that have not really evolved significantly over the past four decades achieving poor results despite being largely adopted.

Figure 2 depicts a common architecture for a power device. Generally the device includes a silicon die 1 that is attached by an attachment 2 to a copper layout 3, which is thermally coupled to a coolant 6 via a substrate 4 and dielectric material 5. Electric current flows mainly laterally in the copper layout 3 but mainly vertically from the die 1 through the attachment 2, layout 3, substrate 4 and dielectric 5. Such an architecture is characterized by relatively poor two- dimensional vectorial thermal propagation in the in the thermal path between the silicon die 1 and the coolant 6. For example, if the coolant 6 is at a temperature of about 80°C, the die 1 is typically at a temperature of 175-200°C due to thermal impedance in the thermal path. The common architecture of Figure 2 can be decomposed by the simplified following thermalimpedance Rth model shown in Figure 3 A and summarized in the table shown Figure 3, B. Figure 3 shows that thermal impedance (Rth) between the die 1 and the coolant 6 is spread into 3 main categories:

1) Dielectric material 5 (Rth4): With a large range of performances and characteristics, dielectric materials must ensure the best thermal conductivity achieving automotive isolation requirements in the order of 4kV for 1 minute, dictating the material thickness therefore Rth.

2) Substrates and mechatronics (Rth2, Rth6, Rth8): Substrates offer mechanical robustness and die mountability as well as exposed surfaces ensuring the thermal continuity to the coolant through the inverter system (mechatronics).

3) Surfaces junction is the point of junction of different elements mounted together and can be categorized in 3 main groups: a) Soldering or sintering diffusion (Rthl) that offer the best thermal conductivity depending on the material used, interface thickness and thermal conductivity. b) Deposition coating of ceramics to metal (e.g., A12O3 flame spray coating) inducing an inter- material interface with its own Rth (Rth3, Rth5) depending of porosity and penetration; c) Pressure contact (Rth7) where 2 surfaces are pressed together to create a thermal path (often the electric path too). This type of interface is highly dependent on the pressure applied, coplanarity, roughness and geometries of the surfaces. It is usually of poor performance and degrades with time.

Though non-intuitive, liquid to solid surface contact (Rth8) is part of this category but is more stable and of better quality/performance depending on the strategy adopted. Laminar flow on a planar surface exhibits a reduced efficiency since only a few molecules at the coolant surface contact to solid will carry the calories to be extracted. The rest of the liquid does not participate actively in the cooling. Turbulent flow creates a greater surface contact area and more carriers but requires a special mechanism to be implemented leading to a greater use of material and system volume increases (i.e., thin fins). As seen above, the total Rth junction to coolant is more an agglomeration of material properties, techniques, and surface area than a single dimension issue. There is a substantial margin for progress. Brief Description of the Drawings

Figures 1 A-1C depict thermal profiles and a side schematics view of different wafer types showing the General Impact of Adding Diamond to Power Electronics in prior art implementations.

Figure 2 depicts a cross section view of a prior art electrical/thermal path in a power device.

Figure 3 A is a thermal impedance Rth model representation of the prior art electrical/thermal path in a power device.

Figure 3B is a table containing relevant values for calculation of the thermal impedance for an example prior art electrical/thermal path in the power device.

Figure 4A is a line graph showing the normalized on-resistance (RdsON) versus temperature of a typical Silicon Carbide (SiC) power device.

Figure 4B is a line graph depicting the saturation voltage across the collector and emitter (VcE(sat)) vs temperature for a typical IGBT device.

Figure 5 is a table summarizing power conduction losses for a 3 -phase 250kW inverter system translated into a standard EV sedan range according to current power device standards

Figure 6 is cross section view of the improved Thermal-Electrical path power devices according to aspects of the present disclosure.

Figure 7 is a thermal impedance Rth model representation of the improved electrical/thermal path power device according to aspects of the present disclosure.

Figure 8 is a table containing relevant values for calculation of the thermal impedance for an example improved electrical/thermal path power device.

Figure 9 is a three-quarter view of a substrate during the method of fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure. Figure 10 is a three-quarter view of transistors attached to the surface of the substrate during the method of fabrication of the improved thermal electric path power devices according to aspects of the present disclosure.

Figure 11 is a three-quarter view of electrically conductive pillar structures coupled to the substrate between the transistor devices during the fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure.

Figure 12 is a side by side, three quarters view depiction of an electrically conductive clip and the substrate having conductive pillars during the fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure.

Figure 13 is a three-quarter view depicting the conductive clip mounted and attached to the transistors on the substrate during the fabrication of the improved thermal electric/path power devices according to aspects of the present disclosure.

Figure 14 is a cut-away three-quarter view showing the mounting and attachment of the conductive to the transistors during the fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure.

Figure 15 is a side-by-side three quarter view showing a thin flex printed circuit board(PCB) for gate connections and the substrate-clip assembly during the fabrication of the improved thermalelectric path power devices according to aspects of the present disclosure.

Figure 16 is a cut away three-quarter view depicting the formation of a bond-wire to the thin flex (PCB) and get pad of a transistor during the fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure.

Figure 17 is a cut-away three-quarter view showing gate driver, control, and sense circuitry mounted on the thin flex PCB coupled to the substrate-clip assembly during the fabrication of the improved thermal-electric path power devices according to aspects of the present disclosure.

Figure 18 is circuit diagram depicting an example gate control circuit layout on thin flex PCB according to aspects of the present disclosure. Figure 19 is diagram depicting two improved thermal-electric path power devices aligned in back-to-back configuration creating an improved half bridge device according to aspects of the present disclosure.

Figure 20 is a diagram depicting formation of epoxy compound in areas of the improved half bridge device according to aspects of the present disclosure.

Figure 21 is a diagram depicting three improved half bridge devices arranged in parallel configuration according to aspects of the present disclosure.

Figure 22 is a diagram depicting bus bars rigidly connecting the three improved half bridge devices in a parallel configuration according to an example of the present disclosure.

Figure 23 is a diagram depicting a cool jet coolant block mounted to the three improved half bridge devices connected via the bus bar according to aspects of the present disclosure.

Figure 24 is a cut-away side view of an improved half bridge device mounted to the cool jet coolant block according to aspects of the present disclosure.

Figure 25 is a cut-away view of a single cool jet cooling block according to aspects of the present disclosure.

Figure 26 is a cut-away view of the side of the cool jet cooling block mounted facing the half bridge device according to aspects of the present disclosure.

Figure 27 is a cut-away side view showing the return side of the cool jet cooling block according to aspects of the present disclosure.

Figure 28 is a diagram showing two coolant blocks, one mounted to each side of the three-phase power inverter according to aspects of the present disclosure.

Figure 29 is a diagram depicting a completed three-phase inverter assembly with motor phase power linkages installed according to aspects of the present disclosure. Figure 30 depicts two coolant blocks mounted to the three-phase inverter having motor phase fasteners coupled to the motor phase power linkages according to aspects of the present disclosure.

Figure 31 shows integrated bulk capacitors and other passive circuitry that may be coupled to the three-phase inverter on a side opposite the motor phase fasteners according to aspects of the present disclosure.

Figure 32 depicts a top-down view of the completed three-phase inverter with cooling block according to aspects of the present disclosure.

Figure 33 shows a side view of the completed three-phase inverter with cooling block according to aspects of the present disclosure.

Figure 34 depicts a simple electric car including the improved three-phase inverter according to aspects of the present disclosure.

Figure 35 is a layout diagram depicting a simple direct drive electrical vehicle using the improved three-phase inverter according to aspects of the present disclosure.

Figure 36 is a layout diagram showing an alternative implementation of the direct drive electric vehicle using the improved three-phase inverter according to aspects of the present disclosure.

Detailed Description

Introduction

The advent and now proven volume scaling and cost reduction of Diamond Foundry’s novel single-crystal diamond wafer enables significant advances in electric vehicle power electronics, improving driving range by up to 5.3% as well as lifetime well beyond 300,000 miles.

Overview

Electronic vehicle (EV) power electronics has increasingly become heat dissipation limited, and the potential range of electronics architectures has been limited by available materials. The thermal stress induced into power semiconductor switches has been a hard call to semiconductor and inverter companies, up to desperation. Engineers across the entire industry have been stuck using materials in their electronics design that do not truly meet the characteristics required for advancing EV power electronics, such in particular including a material that combines extreme thermal conductivity with extreme voltage insulation.

Single-crystal diamond (SCD) is a most extreme material - in multiple dimensions and by a decisive factor each - in particular through its combination of extreme thermal conductivity and extreme electrical insulation. SCD exhibits remarkable dielectric properties including a low dielectric constant of 5.7, a loss tangent below 0.0001 at 35 GHz and a high dielectric strength of 10 MV/cm. This means 20um of SCD can insulate 20kV while at the same time delivering thermal conductivity as high as 3,000 W/mK.

Diamond Foundry, Inc. of South San Francisco, California has achieved production of singlecrystal diamond in wafer dimensions covering the die sizes required by all commercially relevant computer and power-electronics chips.

The Power Traction Inverter Dilemma

An EV’s Power Traction Inverter (PTI) is a critical element of electric mobility. Because of its level of complexity, electrical and thermal stress and eventually cost, PTIs have always been one of the weakest links of the electric mobility implementation, with a remarkable level of failure on the early development of this emerging market, and certainly a technological barrier of entry for OEM adoption. Driving conditions and style often induce substantial electrical and thermal stress to the active components of the inverter and their surrounding elements and if not properly addressed leads to drastic life reduction and eventually failures of the system.

Power inverter advancement has been slow and incremental due to complex design and manufacturing aggravated by custom subsystems requirements, sophisticated integration of high- power electronics, material science, mechatronics, and thermal management. Power density is certainly the key metric of performance for modern power inverters underscoring technology and efficiency. As a reference, state-of-the-art designs exhibit 33kW/L (Tesla Model 3 is 12L, 4.8kg, 400kW) and 36kW/L (Audi e-Tron is 5.5L, 8kg, 200kW). Power semiconductors are essentially driven by two factors: Thermal conductivity - the path to cool them down - and electrical conductivity - the path to carry high currents. Though the electrical path has been worked on for many years with more or less success, the thermal path has always been the main challenge.

Besides the need for high thermal and electrical conductivity, power semiconductors need to be electrically isolated from the rest of the environment because they carry high voltages; this is a safety requirement. Unfortunately, voltage isolation barriers (like DBC substrates) usually demonstrate poor thermal conductivity. Common isolation barriers like high thermal conductivity compounds exhibit 2 to 5 W/mK, state of the art oxides such as Aluminum Oxide (A12O3) show a 24 to 28 W/mK, more modern Aluminum Nitride (AIN) realistically offer 150 to 180 W/mK, therefore keeping a substantial undesirable thermal difference in between the semiconductor junction temperature (Tj) and the cooling mechanism (usually liquid glycol) at the thickness required to ensure electrical isolation.

Power semiconductors such as Silicon Insulated Gate Bipolar Transistors (Si IGBTs) and Silicon Carbide metal oxide semiconductor field effect transistors (SiC MOSFETs) have the same electrical and thermal path through their bottom side unlike other power dissipating devices such as MCU, logic, memory and DSP chips. Today’s most common solution to ensure electrical insulation, and high current carrying capability for Si IGBT and SiC MOSFETs are Direct Bonded Copper (DBC) substrates. Unfortunately, they do not provide high heat carrying capacity.

Diamond Based Power Electronics

Because of its remarkable properties, diamond and diamond based solutions have always been on the far reaching scope of power semiconductors developers. Someone would call it the “Holy Grail” for semiconductors applications. This is the only known material in nature that exhibits ultra-high thermal conductivity and ultra-high band gap. Unlike graphene (another allotrope of carbon) which is electrically conductive, diamond is a premium isolator. Diamond Foundry now offers a practical and cost affordable solution to a very old issue: How to implement a cool down path efficiently to a power semiconductor and insure dielectric isolation at the same time. The advantages of diamond have long been well-known, indeed this not being any surprise or novelty. What is new and disruptive is that Diamond Foundry has now managed to a. produce high-quality single-crystal diamond wafers for all chip die sizes; b. drive down cost to the levels required by automotive power electronics; and c. novel power electronics architectures that fully utilize the capabilities of novel diamond wafers.

Prior work by our team as well as other groups has shown that diamonds reduce peak temperature by as much as 20% for various semiconductors, such reduction improving power efficiency by 10% during such periods.

SCD wafers can be used close to the switching semiconductor device junction in multiple ways: replace ceramics (e.g., Aluminum Oxide (AI2O3), Aluminum Nitride (AIN), Silicon Nitride (Si3N4)) in direct-bonded-copper (DBC) substrates; replace heat spreaders in novel discrete packages; allow for thinning the semiconductor wafer. SCD wafers allow inverter size, weight, and cost reductions based on any and all semiconductor technologies, not requiring a “bet” on a novel form of a semiconductor gaining commercial traction.

The Importance of Sustaining a Lower Junction Temperature

The thermal stress induced into power semiconductor switches yields failure as well as energy efficiency loss. As a general rule of thumb, every 10°C increase in temperature reduces the semiconductor life expectancy by half, setting for example the trend to higher-temperature resilient silicon designs to 200C from 175C for Silicon Carbide power switches. Unlike IGBTs who have an almost constant V _ce (Sat) versus temperature coefficient, MOSFET’s (including SiC) RdsON is a Positive Temperature Depending Parameter (TDP) which means that RdsON increases with temperature.

Figure 4A shows a normalized RdsON for a common SiC device. As the typical RdsON is specified at 25C to be 1 (e.g., 7m0hm) it increases 45% (10.39mOhm) at 150C, 64% (11.64mOhm) at 175C and 90% (12.87 mOh) at 200C. The growth of RdsON vs Tj is split into the linear (25 to 150C) and the exponential region (150 to 200C) meaning that for the same amount of current (400A), the power conduction losses will be 1120W at 25C, 1359W at 100C, 1662W at 150C, 1863W at 175C and 2060W at 200C. Figure 4B shows the V _ce ( _S at) for a typical modern IGBT. Conduction losses at 400A establishes at 800W at 25C, 920W at 125C and 1000W at 150C (no further data available). At the EV’s inverter frequency operation (15kHz), conduction fosses represent about 60% of the cumulated conduction- switching losses of the device. This is mainly due to the so called “tail effect” of IGBT’s and it is directly related to the surface area of the silicon chip. The greater the surface, the bigger the switching losses. Total cumulated conduction and switching losses for IGBTs establishes then to 1375W at 25C, 1580W at 125C and 1720W at 150C. It is remarkable that despite a very slim efficiency advantage to SiC vs IGBTs, the trend of adoption towards SiC is unreversible even the predominant cost of SiC vs IGBTs (about 5X) underscoring that implementation cost is undermined in favor of performances and EV’s range gain.

Since onboard EV’s coolant temperature is set to be 80C as a standard, the challenge here is to keep the Tj as close as possible to coolant to eliminate the unnecessary conduction losses induced by the Tj in the exponential region and part of the linear region too for SiC and allow for a die surface area reduction for IGBTs. Bipolar structures such as IGBTs are quite resilient in respect of forward current as long as temperature dependency latch up conditions are not triggered. It is generally admitted that current density of up to 1000A/cm2 set the limit and IGBTs manufacturer stay usually in the 80 to 90% of this limit over the temperature range. Mastering the junction temperature for IGBTs under the latch up condition enables a substantial die size active area reduction proportionately impacting the switching losses that IGBTs have been suffering since inception. Properly applied thermal management solutions such as Diamond Foundry solutions could see the equalization of modern SiC and antique IGBTs technologies for E-Mobility frequency switching range (10-20kHz) at the 1/5 of the cost.

Specific Impact on EV Driving Range

Figure 5 summarizes the power conduction losses for a 3 -phase 250kW inverter system translated into a standard EV sedan range according to nowadays standards. The 400A per phase current (565 A peak) induced losses are studied across 80C (coolant) to 200C Tj.

The “Inverter Power Losses to be Saved” column shows the energy to be saved from the battery at various Tj, and the range is calculated accordingly from the battery capacity. Assuming the power switches Tj can be kept near by the coolant temperature (80C) the total power losses saving could reach up to 2812W per battery charge or 11.72 miles or 5.33% range increase.

This study is conservative in that it does not take in consideration the regenerative power saving which is estimated to be 15-20% of these figures. This includes power losses temperature dependency in Fast Recovery Diodes (FRD) associated to IGBTs, thermal dependency losses of the SiC MOSFET intrinsic diodes (which exhibit poor performances vs temperature) and the reduction of associated circuitry such as gate driver and collateral components. Size reduction in such proportion open the possibility to a direct integration inverter-motor eradicating power losses in cables length and terminals accounting for another few fractions of percent of the battery capacity.

Beyond Temperature: Enabling Single-Form Factor Architecture for EV Power Electronics

Combining the extraordinary thermal-conductivity, voltage-insulation, and wafer-finish properties of single-crystal diamond wafers, now available from Diamond Foundry, novel device and system designs as well as more efficient assembly processes are enabled that the industry has not yet had the opportunity to pursue for GaN, SiC and IGBTs silicon chips.

In particular, Diamond Foundry’s SCD wafer enables single-form-factor power inverters to exceed lOOOkW/L (e.g., 400kW for a 0.4L system). This comes with a greater system efficiency, losses and system cost reduction translating into energy saving and electric mobility range extension.

A novel thermal management configuration according to aspects of the present disclosure is shown in Figure 6. This configuration delivers a drastic reduction of the thermal impedance elements from nine to four elements. In this configuration, a semiconductor die 1 is attached to a copper substrate 3 by a silver attachment 2. The copper substrate 2 is diffusion bonded to a SCD wafer 7. Diffusion processes used for attachment in between the simplified number of elements constituting the thermal path are now reduced to nanometer scale insuring a free thermal propagation from the semiconductor die 1 through the diamond chip 7 to the coolant 6. The use of the SCD wafer 7 allows for a more three-dimensional thermal propagation, as indicated by the dashed arrows.

One or more pressurized coolant jets 8 deliver coolant 6 to the exposed surface of the diamond wafer 7, offering a perpendicular-impact flow yielding greater performance than laminar, turbulent, or turbulent “thin fins” solution. The corresponding thermal impedance model depicted in Figure 7 in the table depicted and Figure 8 summarize these advantages.

Because the dramatic reduction of total Rth (0.0155 from state of the art ~0.11) the silicon die Tj is now intimately related to the coolant temperature in a lockdown position creating a Tj “clamp” at around 12C above the coolant enabling significant saving in conduction losses compared to those described with respect to Figure 5, optimization of mechanical geometries for the inverter design and the reduction of needed active silicon die surface.

The advanced material and thermal management technology of a configuration like that of Figure 6 offers a drastic reduction in thermal impedance and inverter size reduction paving the way to substantial EV’s range extension, cost reduction and extreme reliability. Furthermore, this technology is scalable and adaptable to similar markets where high power efficiency and reliability is mission critical (i.e. power generation, charging station, grid balancing etc...).

Example Implementation

400kW Power Inverter Design Introduction:

1) Single Switch Description In this example, single switch construction starts with, a 19.5x0.6mm silver (Ag) plated copper Top substrate 102 attached to a 20x0.3mm SCD chip 104. Next, as shown in FIG. 10, three transistors, e.g., IGBTs or MOSFETs are attached to the top substrate, e.g., using Ag sintering technology.

By way of example, and not by way of limitation the MOSFETs 106 may be 130A 1200V silicon carbide (SiC) MOSFET devices formed on 8x8mm silicon chips. Next, as shown in FIG. 11, three electrically conductive pillar structures 108 for the High Current Power Path (V L translator) for the MOSFETs Drain connection are attached to the top substrate. By way of example, and not by way of limitation, the pillar structures may be 6mm width Ag Plated Copper pillars. Next, as shown in FIG. 12, an electrically conductive, e.g., copper, clip 110 is mounted on top of the three SiC MOSFETs and sintered forming the High Current Power Path for the MOSFETs source connection.

As shown in FIG. 13, the clip is mounted and attached to the MOSFETs Source Pad connection, e.g., using sintering technology. Electrical connection to the MOSFETs 106 may be made by sintering top pads 112 on the MOSFETs to corresponding projections 114 on the clip 110, as shown in FIG. 14. A thin flex printed circuit board (PCB) 116 is installed to form a gate router for the MOSFETs’ gate connections 118, as shown in FIG. 15. Conductive extensions 120 on the PCB 116 are electrically connected to the gate connections 118, e.g., by wire bonds 122, as shown in FIG. 16. Thin flex PCB gate driver circuitry 124 and a current sense circuit 126 are added and interconnected with the Gate router 116, as shown in FIG. 17. The corresponding device as an equivalent schematic in FIG. 18.

Subsequently, two identical structures of the type shown in FIG. 17 may be aligned back to back with the SCD chips 104 facing outward, as shown in FIG. 19 and then epoxy compounded 127, as shown in FIG. 20. The epoxied device shown in FIG. 20 may be used in half bridge inverter or for single direction motor control a, so-called Half-H bridge. The sources 110 of each side of the device may be connected in anti-parallel. Each side of the device may also be connected in parallel with a diode to shunt reverse flow of current. The half bridge device may also be integrated into switch mode power supplies using synchronous rectifiers. Two of the half bridge inverter devices may be arranged together to create a full H-bridge for motor control or as a power converter, such as an AC-to-AC converter, DC-to-DC converter, or DC-to-AC converter.

Three half bridge devices may be arranged in parallel as shown below in FIG 21 to create a three-phase inverter device. Each device is aligned with the gate controls located between the source regions for either side of each half bridge device. This parallel arrangement allows short distance rigid connections to be formed between each of the half bridge devices. The three half bridge devices of the type shown in FIG. 21 may be rigidly connected such as via bus bars 128, 129, as shown in FIG. 22. For the three-phase inverter device the drains of each of one side of the three half bridge devices 128 may be connected and the sources on the other side of each of the half bridge devices may be connected 129. The ridged bus bar 128 may form the VBUS (+) bus bar for the three-phase power inverter and the ridge bus bar 129 may form the VBUS (-) bus bar for the three-phase power inverter. The bus bars provide both an electrical connection between half bridge devices and structural rigidity.

The single crystal diamond chip (SCD) 104 allows for efficient cooling of the MOSFETS in each half-bridge device. Cooling blocks 130 may be coupled to each side of the three-phase inverter device as shown in Fig 22. Each of the half bridge devices may include cooling fins for radiative cooling or a fluid interface for liquid or evaporative cooling. The cooling block 130 may be implemented as a cool jet coolant block to provide improved thermal conduction between the coolant and the SCD surface. The cool jet coolant block as shown in Fig 24 uses the venturi effect to jet spray coolant onto the SCD surface creating a high flow rate and a high amount of contact between the cooling liquid and the SCD. As shown the coolant enters the cooling block 130 at the cooling intake port 131. Coolant fills the coolant intake cavity 132 reaching the compression chamber 133. The coolant increases velocity through the venturi 134 and spreads out along the surface of the bell nozzle 135 creating a coolant jet plume that hits the SCD 104. The coolant jet plume may be directed to areas of the SCD 104 that are under a MOSFET 106. Coolant disperses over the SCD 104, moving heat away from the MOSFET 106 and SCD 104. The hot coolant cycles up through the return cavities 136 where it may exit the cooling block 130 and may be cooled before returning to the coolant intake 131. The coolant may be cooled via expansion and radiative cooling through a radiator and fin block. The cooling block 130 may include multiple bell nozzles 135 for example and without limitation, one for each of the MOSFETs 106. As previously discussed, each nozzle 135 may be located such that it is directly behind one of the MOSFETS and directs a jet flow of coolant onto the SCD 104 directly behind the MOSFET. A coolant O-ring seal 137 may prevent the escape of coolant from around the SCD 104.

The front view of FIG. 26 below depicts a view of the side of the cooling block that is mounted facing the three-phase inverter. As shown the cooling block may include three bell nozzles 135 each nozzle configured to behind one of the three MOSFETs of the half bridge device. The return cavities 136 may be located in the space between the bell nozzles 135. FIG 27 shows a cutaway view of the return side of the cooling block according to aspects of the present disclosure. As shown this coolant block includes three nozzle assemblies 139 which are coupled together to cool the three-phase inverter. Coolant blocks may include any number of nozzles assemblies sufficient to cool inverter devices including the half bridge devices according to aspects of the present disclosure. There is a return cavity 136 for a side of each of the corresponding half bridge devices and each return path is connected allowing coolant to flow to the coolant outlet port 138.

FIG. 28 shows a three-phase inverter that utilizes two coolant blocks, with one mounted to each side of the three-phase power inverter and configured to cool a side of each of the three half bridge devices in the three-phase inverter. FIG. 29 depicts a completed three-phase inverter assembly with the motor phase power linkages installed 140. The motor phase power linkages 140 connect the drain and source of each half bridge device such that current only flows when one side of the half bridge device is in the on-state. Fig. 30 depicts two coolant blocks mounted to the three-phase inverter having motor phase fasteners 141 coupled to the motor phase power linkages 140. Fig. 31 shows integrated bulk capacitors and other passive circuitry 142 that may be coupled to the three-phase inverter on a side opposite the motor phase fasteners 141.

FIG 32 depicts a top-down view of the completed three-phase inverter with cooling block according to aspects of the present disclosure. As shown the three-phase inverter includes motor phase fasteners 141, bus bars 129, 128, and the cooling blocks 130 include coolant inlet ports 131 and coolant outlet ports 138. Figure 33 shows a side view of the completed three-phase inverter with cooling block according to aspects of the present disclosure. In the side view the motor phase power linkages 140, half bridge device 143 and passive circuitry 142 can also be seen.

According to additional aspects of the present disclosure the three-phase inverter device may be integrated into an electric vehicle for example an electric car, plane, helicopter, train, ship, or submarine.

Fig. 34 depicts a simple electric car including the three-phase inverter according to aspects of the present disclosure. As shown, the simple electric car may include the three-phase inverter and coolant block assembly 201 coupled to a three-phase electric motor 202. Each of the phases of the electric motor 202 may be conductively coupled to a motor phase fastener of the three-phase inverter 201. The output shaft of the electric motor 202 may be coupled to a differential (and optionally a gearbox) 203 configured to apply rotational velocity to the axel 204 connected the drive wheels 205. The three-phase inverter takes direct current (DC) electricity from a battery or other power source 206 and converts it to three-phase power which the electric motor 202 can turn into rotational velocity of its output shaft. A controller 208 may be coupled to the three- phase inverter and be configured to control the phases to operate the electric motor. The battery or other power source 206 may receive electricity from a charging circuit 207 which may receive electricity from an outside source such as AC electricity from a wall outlet. The charging circuit 207 may be for example an AC-to-DC converter and may utilize half bridge devices described in the present disclosure. The coolant blocks of the three-phase inverter may be coupled to a coolant system including a radiator 209 and coolant pump 210. For stability the electric car may also include additional wheels 211.

FIG. 35 depicts a simple direct drive electrical vehicle such as an electric motorcycle. Unlike the electrical car depicted in FIG 34 the direct drive electrical vehicle omits a differential and instead the electric motor 202 directly drives the drive wheels 205. A direct drive electrical vehicle may include an electrical motor 202 and three-phase inverter 201 for each of the drive wheels 205 according to aspects of the present disclosure. A direct drive vehicle according to aspects of the present disclosure may include any number of drive wheels having corresponding electrical motors and inverters. According to some additional aspects of the present disclosure multiple electric motors may be coupled to a three-phase inverter.

Fig. 36 shows an alternative embodiment of the direct drive electric vehicle. In the vehicle shown, the three-phase inverter 201 drives, an electric motor 202 connected to a propellor, liquid screw or other device use to generate thrust 220 through a liquid. This embodiment may be implemented many vehicles such as planes, boats, submarines, helicopters, quadcopters etc. In some implementation multiple electric motors 202 and inverters 201 may be included on the same coolant loop and share a radiator 209 and coolant pump 210.

Glossary

MOSFET: Metal Oxide Field Effect Transistor: A power Switch

IGBT: Insulated Gate Bipolar Transistor: A power Switch

V _ce (Satf Voltage Collector-Emitter when Saturated

RdsON: Resistance Drain Source ON state of a MOSFET transistor

PTI’s: Power Traction Inverters

OEM: Original Equipment Manufacturer (i.e. a car brand/manufacturer)

DC: Direct Current

AC: Alternating Current kW: Kilo Watt, 1000 Watts MW: Mega Watts, 1000 kW SAC305: A solder paste Sn(tin) Ag(Silver) Cu(Copper) respectively 97,3, 0.5% mixt W/mK: Watts per meters (in 3 dimensions) per Kelvin, a measure of thermal impedance IMS: Insulated Metal Substrate

Rth: Thermal Impedance kV: Kilo Volts, 1000 Volts

SiC: Silicon Carbide, a technology used to produce transistors mOhm: Milli Ohm, an Ohm divided by 1000.

Tj: Temperature Junction, the temperature of a silicon chip