Title:
DICING METHOD FOR MULTI-LAYER STACKED WAFER, AND MULTI-LAYER STACK STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2024/087392
Kind Code:
A1
Abstract:
Disclosed in the present disclosure is a dicing method for a multi-layer stacked wafer. The method comprises the following steps: forming a first stack structure located on a first base, and a second stack structure stacked on the first stack structure, wherein the first stack structure comprises a plurality of wafers arranged in a stacked manner in a first direction, and the second stack structure comprises a plurality of first sacrificial layers arranged in a stacked manner in the first direction; forming, in the second stack structure, an opening which penetrates the second stack structure in the first direction; and taking, one by one, the plurality of first sacrificial layers in the second stack structure as an etching cut-off layer for etching the plurality of wafers in the first stack structure, and sequentially dicing the plurality of wafers in the first stack structure along the opening, so as to form a dicing recess which penetrates the first stack structure in the first direction. By means of the present disclosure, particulate matters and residual stress generated during the process of dicing the first stack structure can be reduced.
Inventors:
FANG QINGCHUN (CN)
Application Number:
PCT/CN2023/070466
Publication Date:
May 02, 2024
Filing Date:
January 04, 2023
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
H01L21/304
Foreign References:
| CN114446876A | 2022-05-06 | |||
| CN109192717A | 2019-01-11 | |||
| JP2005244040A | 2005-09-08 |
Attorney, Agent or Firm:
SHANGHAI WINSUN INTELLECTUAL PROPERTY AGENCY (CN)
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