TECHNICAL FIELD

The present disclosure relates generally to the field of wired communication; and more specifically, to a differential amplifier for use in a wired or an optical communication system, a transmitter unit with the differential amplifier, and a receiver unit with the differential amplifier.

BACKGROUND

Generally, a differential pair is used to amplify a differential input signal (i.e. a difference of two input signals). Typicallly, the differential pair includes a pair of either bipolar junction transistors (BJTs) or complementary metal oxide semiconductor (CMOS) transistors. Alternatively stated, a conventional differential amplifier includes the differential pair of either BJTs or CMOS transistors. However, the conventional differential amplifier is a single stage amplifier that provides less amplification gain and bandwidth and hence, finds limited use for high data rate applications. Moreover, the conventional differential amplifier (e.g. the single stage amplifier) experiences a miller effect at high frequencies, which results in its performance degradation. Typically, in the miller effect, capacitance of a capacitor (i.e. C _m ), connected at input nodes of each transistor of the conventional differential amplifier, increases by virtue of an amplification (or inverting) gain (i.e. a base-to-collector gain) of each transistor. This in turn, reduces the bandwidth of the conventional differential amplifier and limits the operation of the amplifier to lower frequencies.

Currently, certain attempts have been made to mitigate the miller effect by use of a conventional cascode amplifier. The conventional cascode amplifier is a two-stage amplifier in which an input stage (i.e. a differential pair) is connected in series with a cascode stage. The input stage includes a pair of input transistors (i.e. Q, _n ) that provides a transconductance gain (i.e. g _m ) to translate an input voltage differential signal (i.e. v, _n ) into a differential current signal (i.e. i, _n ) according to the following mathematical expression (equation 1): i _in = g _m ^v in (^), where the cascode stage acts as a buffer stage for the differential current signal (i _m ). The cascode stage decouples the input voltage differential signal (v, _n ) from output nodes by providing isolation and a voltage gain is provided by loads (i.e. resistors). Typically, a bandwidth limitation of the cascode stage (i.e. a gain stage) comes from a resistor-capacitor (RC) pole at the output. The real cut off frequency is determined by the following mathematical expression (equation 2): f—3c _LB = refers to the real cut off frequency. Additionally, a capacitor (i.e. C _m ) connected between input nodes of transistors of the input stage and source of the cascode stage is exposed to the Miller effect. The input stage provides an inverting gain, therefore, real value of the capacitor (C _m ) is virtually increased by a base-to-collector gain of the input transistors (Q _m ). Although, the conventional cascode amplifier mitigates the miller amplification effect to some extent by reducing the gain across the capacitor C _m , however, the limited bandwidth and the less residual base-to-collector gain of the conventional cascode amplifier limits its use for high data rate applications (e.g. ultra-high-band applications). Thus, there exists a technical problem of an inefficient differential amplifier used in a conventional transmitter unit or in a conventional receiver unit that manifests reduced gain and bandwidth and fails to adequately mitigate the miller effect for use in a high data-rate wired or optical communication system.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional differential amplifier, and the conventional transmitter unit and receiver unit that uses the conventional differential amplifier.

SUMMARY

The present disclosure seeks to provide a differential amplifier, a transmitter unit with the differential amplifier, and a receiver unit with the differential amplifier, for high performance data communication in a wired or an optical communication system. The present disclosure seeks to provide a solution to the existing problem of an inefficient differential amplifier used in a conventional transmitter unit or a conventional receiver unit that manifests reduced gain and bandwidth and fails to adequately mitigate the miller effect for use in a wired or an optical communication system for high data-rate applications. An aim of the present disclosure is to provide a solution that overcomes at least partially the problems encountered in prior art, and provides an improved differential amplifier, an improved transmitter unit and receiver unit with the differential amplifier, for use in the wired or optical communication system for high data-rate applications.

The object of the present disclosure is achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides a differential amplifier having an input stage comprising a first input transistor and a second input transistor, each input transistor having a first, a second and a third terminal being a base, an emitter and a collector, respectively or a gate, a source and a drain, respectively. The first terminal of the first input transistor and the first terminal of the second input transistor constituting input terminals of the differential amplifier. The second terminal of the first input transistor and the second terminal of the second input transistor being interconnected, each input transistor having a parasitic capacitance between its third and its first terminal. The differential amplifier further comprises a first capacitor coupled between the first terminal of the first input transistor and the third terminal of the second transistor, and a second capacitor coupled between the first terminal of the second input transistor and the third terminal of the first input transistor, for cancelling out the parasitic capacitance of each input transistor at least partially. The differential amplifier further comprises one or more cascode stages, each cascode stage comprising a first and a second cascode transistor, and each cascode transistor having a first, a second and a third terminal. The first cascode stage being connected in series with the input stage in such a way that the first cascode transistor is connected by its second terminal to the third terminal of the first input transistor and the second cascode transistor is connected by its second terminal to the third terminal of the second input transistor. The first transistors of the input stage and the one or more cascode stages forming a first side of the differential amplifier and the second transistors of the input stage and the one or more cascode stages forming a second side of the differential amplifier. The differential amplifier further comprises a first inductor pair comprising a first inductor and a second inductor, the first inductor pair being connected between the input stage and the first cascode stage or between the first cascode stage and a subsequent cascode stage, the first inductor being connected on the first side of the differential amplifier and the second inductor being connected on the second side of the differential amplifier.

The differential amplifier of the present disclosure provides an improved amplification gain and an extended bandwidth (i.e. an improved data bandwidth). The disclosed differential amplifier nullifies the miller effect (i.e. amplification of base-to-collector capacitor) by use of a miller negative capacitor (i.e. C _m ). The miller negative capacitor (i.e. C _m ) also allows to limit the input capacitive load of an implication stage (e.g. input stage). The disclosed differential amplifier mitigates the miller effect by use of the miller negative capacitor (C _m ), therefore, the amplification gain (i.e. base-to-collector gain) of input transistors of the input stage does not reduce significantly. The one or more cascode stages in the disclosed differential amplifier adds an extra degree of freedom that allows to include inter-stage inductors (i.e. the first inductor pair). The first inductor pair being connected between the first cascode stage and the subsequent cascode stage (i.e. a current buffer stage) enables the disclosed differential amplifier to achieve an improved bandwidth that can be applied to the design of a broad-band driver amplifier for a high performance data communication (i.e. improved data-rate) in a wired or an optical communication system. For example, wideband driver amplifiers (DRVs) and wideband transimpedance amplifiers (TIAs) for the high data-rate wired or optical communication system.

In an implementation form, the first inductor pair is connected between the input stage and the first cascode stage.

In the disclosed differential amplifier, the first inductor pair creates a resonant network with the parasitic capacitance of the input stage and has a high-quality factor (i.e. a high Q factor) without any penalties or side effects. This resonant network resonates the reactance of the parasitic capacitance and hence performs what is commonly known as reactive amplification, since it eliminates the effect of the low pass pole on the gain, due to the reactance of the capacitances. The quality factor (or the Q factor) is a measure of quality of the resonant network. The high- quality factor (or the high Q factor) of the resonant network indicates an improved data bandwidth which is desirable for high performance data communication in a wired or an optical communication system.

In a further implementation form, the differential amplifier further comprises a second inductor pair comprising a third inductor and a fourth inductor, the second inductor pair being connected between two consecutive cascode stages, the third inductor being connected on the first side of the differential amplifier and the fourth inductor being connected on the second side of the differential amplifier.

The second inductor pair (or inter-stage inductors) improves data bandwidth in the differential amplifier. The second inductor pair creates a resonant network with a parasitic capacitance (i.e. C _p ) and allows the disclosed differential amplifier to achieve a further reactive amplification gain in addition to that due to the first inductor pair.

In a further implementation form, the differential amplifier further comprises two or more cascode stages connected in series, wherein the first inductor pair is connected between two cascode stages.

The two or more cascode stages provides an extra degree of freedom to optimize an input impedance of the input stage which is useful in an amplification chain of various amplifiers for a high bandwidth application. For example, the amplification chain of various amplifiers (including the disclosed differential amplifier) may be provided in receivers (e.g. transimpedance amplifiers (TIAs)) and transmitters (e.g. drivers (DRVs)) for optical communications and broad band monolithic integrated circuit. In a further implementation form, the input transistors and the cascode transistors are bipolar junction transistors and the first, second and third terminals are a base, an emitter, and a collector, respectively.

It is advantageous to have the input transistors and the cascode transistors as bipolar junction transistors because they assist the differential amplifier to operate in a high bandwidth application.

In a further implementation form, the input transistors and the cascode transistors are CMOS transistors and the first, second and third terminals are a gate, a source, and a drain, respectively.

This is advantageous to have the input transistors and the cascode transistors as CMOS transistors because of their infinite input impedance which further assists the differential amplifier to achieve high amplification gain.

In another aspect, the present disclosure provides a transmitter unit having a transmit path comprising the differential amplifier according to the first aspect and its various implementation forms.

The transmitter unit achieves all the advantages and effects of the differential amplifier of the present disclosure. The transmitter unit acts as a wideband driver amplifier for use in a high data rate wired or optical communication system.

In an implementation form, the differential amplifier is connected between a pre-driver and a modulator.

In the transmit path of the transmitter unit, the differential amplifier acts as a linear broadband driver. The linear broadband driver operates in collaboration with the pre-driver and provides a collective amplification gain that is required to achieve a high linear output voltage swing and to drive the modulator (e.g. an optical modulator).

In another aspect, the present disclosure provides a receiver unit comprising the differential amplifier of the present disclosure and its various implementation forms.

The receiver unit achieves all the advantages and effects of the differential amplifier of the present disclosure. The receiver unit acts as a wideband transimpedance amplifier (TIA) when used in a high data rate wired or optical communication system. In an implementation form, the differential amplifier is connected after a low noise amplifier and or a variable gain amplifier preventing to limit the cascaded total bandwidth of the system.

In the receive path of the receiver unit, the differential amplifier acts as a post-amplifier to overcome the noise of subsequent parts of the receiver unit. Moreover, the post-amplifier provides a sufficient amplification gain along with gain of the low noise amplifier and or with the variable gain amplifier to avoid the degradation of sensitivity of the receiver unit at high bandwidth.

It has to be noted that all devices, elements, circuitry, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein: FIG. 1A is a circuit diagram of a differential amplifier, in accordance with an embodiment of the present disclosure;

FIG. 1 B is a circuit diagram of a resonant network, in accordance with an embodiment of the present disclosure;

FIG. 1C is a graphical representation that illustrates a frequency response of a differential amplifier, in accordance with an embodiment of the present disclosure;

FIG. 1 D is a circuit diagram of cross coupling of input capacitors, in accordance with an embodiment of the present disclosure;

FIG. 1 E is a circuit diagram of a differential amplifier, in accordance with another embodiment of the present disclosure;

FIG. 2 is a circuit diagram of a differential amplifier, in accordance with yet another embodiment of the present disclosure;

FIG. 3 is a circuit diagram of a differential amplifier, in accordance with another embodiment of the present disclosure;

FIG. 4 is a block diagram that illustrates various exemplary components of a transmitter unit, in accordance with an embodiment of the present disclosure; and

FIG. 5 is a block diagram that illustrates various exemplary components of a receiver unit, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non- underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practicing the present disclosure are also possible. FIG. 1 A is a circuit diagram of a differential amplifier, in accordance with an embodiment of the present disclosure. With reference to FIG. 1A, there is shown a circuit architecture of a differential amplifier 100A that includes an input stage 102. The input stage 102 includes a first input transistor 104 and a second input transistor 106. The differential amplifier 100A further includes a current circuitry 108, a ground terminal 110, a first capacitor 112, a second capacitor 114 and a first cascode stage 116. The first cascode stage 116 includes a first cascode transistor 118 and a second cascode transistor 120. The differential amplifier 100A further includes a first side 122, a second side 124, a first inductor pair 126 and a second cascode stage 128. The first inductor pair 126 includes a first inductor 126A and a second inductor 126B. The second cascode stage 128 includes a first cascode transistor 130 and a second cascode transistor 132. The differential amplifier 100A further includes a second inductor pair 134. The second inductor pair 134 includes a third inductor 134A and a fourth inductor 134B.

The differential amplifier 100A has an input stage 102 comprising the first input transistor 104 and a second input transistor 106, each input transistor having a first, a second and a third terminal being a base, an emitter and a collector, respectively or a gate, a source and a drain, respectively. The first terminal 104A of the first input transistor 104 and the first terminal 106A of the second input transistor 106 constituting input terminals of the differential amplifier 100A. The second terminal 104B of the first input transistor 104 and the second terminal 106B of the second input transistor 106 being interconnected, each input transistor having a parasitic capacitance between its third and its first terminal. The input stage 102 includes a differential pair (i.e. the first input transistor 104 and the second input transistor 106) or an input transistor pair (e.g. Q _m ) for providing a transconductance gain (e.g. g _m ) to translate an input voltage differential signal (e.g. V _m ) into a differential current signal (e.g. i _m ). The input voltage differential signal (V _m ) is applied to the first terminal 104A (i.e. a base) of the first input transistor 104 and the first terminal 106A (i.e. another base) of the second input transistor 106 as +Vin/2 and -V _m /2, respectively, for conversion into the differential current signal (i _m ). The second terminal 104B (i.e. an emitter) of the first input transistor 104 and the second terminal 106B (i.e. another emitter) of the second input transistor 106 are further connected to the current circuitry 108 (e.g. a constant current source) and the ground terminal 110 to maintain a constant current throughout the differential amplifier 100A. The first (e.g. the first terminal 104A of the first input transistor 104 and the first terminal 106A of the second input transistor 106) and the third terminals (e.g. the third terminal 104C of the first input transistor 104 and the third terminal 106C of the second input transistor 106) of each input transistor (e.g. the first input transistor 104 and the second input transistor 106) are made up of a conducting material (e.g. a metal), therefore, there is always a capacitance associated with the terminals (e.g. the terminals 104A, 106A, 104C and 106C) and the capacitance is known as the parasitic capacitance (i.e. the capacitor C _m between base to collector of each input transistor) and described in detail, for example, in FIG. 1D.

The differential amplifier 100A further comprises the first capacitor 112 coupled between the first terminal 104A of the first input transistor 104 and the third terminal 106C of the second transistor 106, and the second capacitor 114 coupled between the first terminal 106A of the second input transistor 106 and the third terminal 104C of the first input transistor 104, for cancelling out the parasitic capacitance of each input transistor at least partially. The first capacitor 112 (i.e. C _m ) and the second capacitor 114 (i.e. C _m ) are configured to counteract the miller effect (i.e. amplification of capacitor (C _m ) due to a base-to-collector gain) in the differential amplifier 100A. The first capacitor 112 (C _m ) and the second capacitor 114 (C _m ) reduces the base-to-collector gain across the capacitor (C _m ), at input nodes of each transistor of the input stage 102. The working of the first capacitor 112 (C _m ) and the second capacitor 114 (Ci _n ) is described in detail, for example, in FIG. 1D.

The differential amplifier 100A further comprises one or more cascode stages, each cascode stage comprising a first and a second cascode transistor, each cascode transistor having a first, a second and a third terminal, the first cascode stage 116 being connected in series with the input stage 102 in such a way that the first cascode transistor 118 is connected by its second terminal 118B to the third terminal 104C of the first input transistor 104 and the second cascode transistor 120 is connected by its second terminal 120B to the third terminal 106C of the second input transistor 106. The first transistors of the input stage 102 and the one or more cascode stages forms a first side 122 of the differential amplifier 100A and the second transistors of the input stage 102 and the one or more cascode stages forms a second side 124 of the differential amplifier 100A. The first cascode stage 116 (i.e. Q _c ) acts as a buffer stage for the differential signal current (i _m ). The signal current (i, _n ) at the first cascode transistor 118 (i.e. Q _d ) becomes a part of a resonant network which further results in the reactive amplification and an improved bandwidth of the differential amplifier 100A and is described in detail, for example, in FIG. 1B.

The differential amplifier 100A further comprises a first inductor pair 126 comprising a first inductor 126A and a second inductor 126B, the first inductor pair 126 being connected between the input stage 102 and the first cascode stage 116 or between the first cascode stage 116 and a subsequent cascode stage 128, the first inductor 126A being connected on the first side 122 of the differential amplifier 100A and the second inductor 126B being connected on the second side 124 of the differential amplifier 100A. The first inductor pair 126 includes the first inductor 126A (i.e. ) and the second inductor 126B (i.e. ) which create the resonant network that provides the reactive amplification of the input signal current (i.e. the differential current signal (i _m )). The resonant network is further exploited to achieve a bandwidth extension.

In accordance with an embodiment, the first inductor pair 126 is connected between the input stage 102 and the first cascode stage 116. The first inductor pair 126 improves the reactive amplification gain and bandwidth of the differential amplifier 100A by virtue of the resonant network, described in detail, for example, in FIGs. 1B and 1C.

In accordance with an embodiment, the differential amplifier 100A further comprises a second inductor pair 134 comprising a third inductor 134A and a fourth inductor 134B, the second inductor pair 134 being connected between two consecutive cascode stages, the third inductor 134A being connected on the first side 122 of the differential amplifier 100A and the fourth inductor 134B being connected on the second side 124 of the differential amplifier 100A. The second inductor pair 134 includes the third inductor 134A (i.e. L2) and the fourth inductor 134B (i.e. L2) which operates between two current buffers (i.e. the first cascode stage 116 and the second cascode stage 128), therefore, the differential amplifier 100A has the high quality factor (or the high Q factor) without any penalties or side effects, where the high quality factor indicates an improvement in bandwidth of the differential amplifier 100A.

In accordance with an embodiment, the differential amplifier 100A further comprises two or more cascode stages connected in series, wherein the first inductor pair 126 is connected between two cascode stages. The two or more cascode stages adds an extra degree of freedom that allows to include two inter-stage inductors ( and L2) in the differential amplifier 100A. The extra degree of freedom refers to the number of values involved in a calculation and which are free to vary.

In accordance with an embodiment, the input transistors and the cascode transistors are bipolar junction transistors and the first, second and third terminals are a base, an emitter and a collector, respectively. The input transistors and the cascode transistors of the differential amplifier 100A are bipolar junction transistors (BJTs). A Bipolar junction transistor (BJT) is a three-terminal device which has two p-n junctions and acts as an amplifier. The first input transistor 104 has the first terminal 104A as the base, the second terminal 104B as the emitter and the third terminal 104C as the collector, respectively. Same is with the second input transistor 106 and the cascode transistors. In accordance with an embodiment, the input transistors and the cascode transistors are CMOS transistors and the first, second and third terminals are a gate, a source, and a drain, respectively. In an implementation, the input transistors and the cascode transistors can be complementary metal oxide semiconductor (CMOS) transistors. A CMOS transistor is a three- terminal device with the first terminal as the gate, the second terminal as the source and the third terminal as the drain, respectively and is described in detail, for example, in FIG. 2.

Thus, as the differential amplifier 100A includes the double cascode stage (i.e. the first cascode stage 116 and the second cascode stage 128) with the inter-stage inductors (i.e. the first inductor pair 126 and the second inductor pair 134) and the miller negative capacitance (i.e. the first capacitor 112 and the second capacitor 114) at input side hence, the differential amplifier 100A provides a high amplification gain and a high data bandwidth which is desirable for a high data-rate wired or optical communication system. For example, the differential amplifier 100A when potentially used in a transmitter unit (e.g. wideband driver amplifier), described in detail, for example, in FIG. 4, provides a high data-rate and high gain as well. Similarly, the differential amplifier 100A when potentially used in a receiver unit (e.g. wideband transimpedance amplifier), described in detail, for example, in FIG. 5, provides high data-rate and high gain together.

FIG. 1 B is a circuit diagram of a resonant network, in accordance with an embodiment of the present disclosure. FIG. 1B is described in conjunction with elements from FIG. 1A. With reference to FIG. 1B, there is shown a circuit architecture 100B that includes a resonant network 136, which is used in a differential amplifier, such as the differential amplifier 100A (of FIG. 1A). The resonant network 136 includes a capacitor 138.

The resonant network 136 includes suitable logic, circuitry, interfaces and/or code that is configured to have a very low impedance at a certain frequency. In an example, the resonant network 136 is a network of an inductor such as the third inductor 134A (L2) (of the second inductor pair 134 of the differential amplifier 100A) which is connected in parallel to a capacitor such as the capacitor 138 (i.e. C _p ). The third inductor 134A (L2) acts as an inter-stage inductor between the first cascode transistor 118 (Q _ci ) of the first cascode stage 116 and the first cascode transistor 130 (Q _C 2) of the second cascode stage 128. The third inductor 134A (i.e. the inter-stage inductor (L2)) is connected at the third terminal 118C (i.e. a collector) of the first cascode transistor 118 (Q _ci ) and the second terminal 130B (i.e. an emitter) of the first cascode transistor 130 (Q _C 2). The third inductor 134A (i.e. the inter-stage inductor (L2)) is used to improve the bandwidth of the differential amplifier 100A (of FIG. 1A) by virtue of the resonant network 136 with the capacitor 138. As the resonant network 136 approaches towards a resonant frequency (i.e. the frequency at which the impedance is minimum), the differential signal current (i _m ) at the first cascode transistor 118 become a part of the resonant network 136 and gets reactive amplification gain and this effect is further used to extend the bandwidth of the differential amplifier 100A. In this embodiment, the first side 122 of the differential amplifier 100A is considered and same scenario will be applicable on the second side 124 of the differential amplifier 100A.

FIG. 1C is a graphical representation that illustrates a frequency response of a differential amplifier, in accordance with an embodiment of the present disclosure. FIG. 1C is described in conjunction with elements from FIGs. 1A and 1B. With reference to FIG. 1C, there is shown a graphical representation 100C that illustrates a frequency response of the differential amplifier 100A (of FIG. 1A). The graphical representation 100C includes an X-axis 140A that represents frequency and a Y-axis 140B that represents transfer function of the differential amplifier 100A.

In the graphical representation 100C, a first line 142 represents the frequency response of the differential amplifier 100A. The first line 142 includes a circular region 142A which indicates the frequency response of the differential amplifier 100A at a resonant frequency (or a cut-off frequency). The frequency response of the differential amplifier 100A is flat before the circular region 142A. As the resonant network 136 (of FIG. 1B) of the differential amplifier 100A approaches at the resonant frequency (or the cut-off frequency), the frequency response (represented by the first line 142) indicates a hike 142B in the circular region 142A which denotes an increase in the amplification gain and bandwidth of the differential amplifier 100A. The hike 142B indicates an improved bandwidth (i.e. greater than -3dB bandwidth) of the differential amplifier 100A as compared to the conventional cascode differential amplifier.

FIG. 1D is a circuit diagram of cross coupling of input capacitors, in accordance with an embodiment of the present disclosure. FIG. 1D is described in conjunction with elements from FIG. 1A. With reference to FIG. 1D, there is shown a circuit architecture 100D that includes a first parasitic capacitor 112A and a second parasitic capacitor 114A.

In accordance with an embodiment, the first parasitic capacitor 112A (C _m ) exists between the first terminal 104A (i.e. a base) and the third terminal 104C (i.e. a collector) of the first input transistor 104. Similarly, the second parasitic capacitor 114A (C _m ) exists between the first terminal 106A (i.e. a base) and the third terminal 106C (i.e. a collector) of the second input transistor 106. The first parasitic capacitor 112A (C _m ) and the second parasitic capacitor 114A (C _m ), are exposed to the miller effect and in turn, collectively, reduce the bandwidth of the differential amplifier 100A. Therefore, to counteract against the miller amplification of the first parasitic capacitor 112A (C _m ) and the second parasitic capacitor 114A (C _m ), the first capacitor 112 (Ci _n ) and the second capacitor 114 (C _m ) are connected in a cross-coupling configuration across the first input transistor 104 and the second input transistor 106. The first capacitor 112 (Ci _n ) and the second capacitor 114 (C _m ) are connected across a positive amplification and by setting the value of capacitors as C _m > C _m , the input load capacitor can become negative. Therefore, the first capacitor 112 (C _m ) and the second capacitor 114 (C _m ) are also known as miller negative capacitors. The differential amplifier 100A (of FIG. 1A) includes the first cascode stage 116 (i.e. the gain stage), therefore, the cross coupling of the first capacitor 112 (Ci _n ) and the second capacitor 114 (C _m ) is beneficial for the input stage 102 (or the driving stage) because its capacitive load can be strongly reduced.

FIG. 1E is a circuit diagram of a differential amplifier, in accordance with another embodiment of the present disclosure. FIG. 1E is described in conjunction with elements from FIG. 1A. With reference to FIG. 1E, there is shown a circuit architecture of a differential amplifier 100E.

The differential amplifier 100E corresponds to the differential amplifier 100A (of FIG. 1A) except a difference. The difference is that, in the differential amplifier 100E, the first inductor pair 126 of the differential amplifier 100A (of FIG. 1A) is removed. Thus, the differential amplifier 100E is more cost-effective. The differential amplifier 100E is an alternative implementation of the differential amplifier 100A after the removal of the first inductor pair 126 (of FIG. 1A) between the input stage 102 and the first cascode stage 116.

FIG. 2 is a circuit diagram of a differential amplifier, in accordance with another embodiment of the present disclosure. FIG. 2 is described in conjunction with elements from FIG. 1A. With reference to FIG. 2, there is shown a circuit architecture of a differential amplifier 200 that includes an input stage 202. The input stage 202 includes a first input transistor 204 and a second input transistor 206. The differential amplifier 200 further includes a current circuitry 208, a ground terminal 210, a first capacitor 212, a second capacitor 214 and a first cascode stage 216. The first cascode stage 216 includes a first cascode transistor 218 and a second cascode transistor 220. The differential amplifier 200 further includes a first side 222, a second side 224, a first inductor pair 226 and a second cascode stage 228. The first inductor pair 226 includes a first inductor 226A and a second inductor 226B. The second cascode stage 228 includes a first cascode transistor 230 and a second cascode transistor 232. The differential amplifier 200 further includes a second inductor pair 234. The second inductor pair 234 includes a third inductor 234A and a fourth inductor 234B. The differential amplifier 200 corresponds to the differential amplifier 100A except a difference (i.e. a modification). The difference is that, in the differential amplifier 200, the input transistors (Min) and the cascode transistors (M _ci and M _C 2) are CMOS transistors and the first, second and third terminals are a gate, a source, and a drain, respectively. However, in the differential amplifier 100A (of FIG. 1A), the input transistors (Q, _n ) and the cascode transistors (Q _ci and Q _C 2) are bipolar junction transistors (BJT) and the first, second and third terminals are a base, an emitter and a collector, respectively. The differential amplifier 200 is a second alternative implementation of the differential amplifier 100A (of FIG. 1A). In the differential amplifier 200, the input transistors (Mm) and the cascode transistors (M _ci and M _C 2) being CMOS transistors have infinite input impedance which results in high amplification gain. A complementary metal oxide semiconductor (CMOS) transistor includes a P-channel (PMOS) and an N-channel (NMOS) transistors. The term MOS in CMOS is an abbreviation of MOSFET (i.e. metal oxide semiconductor field effect transistor). The P-channel MOSFET includes P-type source and drain both of which are diffused on a N-type substrate and majority charge carriers are holes. Similarly, the N-channel MOSFET includes N-type source and drain both of which are diffused on a P-type substrate and majority charge carriers are electrons.

Working and connections of the input stage 202, the current circuitry 208, the ground terminal 210, the first capacitor 212, the second capacitor 214, the first cascode stage 216, the first inductor pair 226, the second cascode stage 228 and the second inductor pair 234, of the differential amplifier 200 is same that has been described in detail, for example, in FIG. 1A and hence omitted here for the sake of brevity.

FIG. 3 is a circuit diagram of a differential amplifier, in accordance with another embodiment of the present disclosure. FIG. 3 is described in conjunction with elements from FIGs. 1A, 1E and 2. With reference to FIG. 3, there is shown a circuit architecture of a differential amplifier 300 that includes an input stage 302. The input stage 302 includes a first input transistor 304 and a second input transistor 306. The differential amplifier 300 further includes a current circuitry 308, a ground terminal 310, a first capacitor 312, a second capacitor 314 and a first cascode stage 316. The first cascode stage 316 includes a first cascode transistor 318 and a second cascode transistor 320. The differential amplifier 300 further includes a first side 322, a second side 324 and a second cascode stage 326. The second cascode stage 326 includes a first cascode transistor 328 and a second cascode transistor 330. The differential amplifier 300 further includes a second inductor pair 332. The second inductor pair 332 includes a third inductor 332A and a fourth inductor 332B. In the differential amplifier 300, the input transistors (M _m ) of the input stage 302 are CMOS transistors. The cascode transistors (Q _ci and Q _C 2) of the first cascode stage 316 and the second cascode stage 326 respectively, are bipolar junction transistors (BJT). Therefore, the differential amplifier 300 is a bipolar CMOS (BiCMOS) implementation of the differential amplifier 100A (of FIG. 1A). In the differential amplifier 300, there is no inductor pair (e.g. the first inductor pair) between the input stage 302 and the first cascode stage 316.

Working and connections of the input stage 302, the current circuitry 308, the ground terminal 310, the first capacitor 312, the second capacitor 314, the first cascode stage 316, the second cascode stage 326 and the second inductor pair 332, of the differential amplifier 300 is same that has been described in detail, for example, in FIG. 1 A and hence omitted here for the sake of brevity.

FIG. 4 is a block diagram that illustrates various exemplary components of a transmitter unit, in accordance with an embodiment of the present disclosure. FIG. 4 is described in conjunction with elements from FIGs. 1A, 1E, 2 and 3. With reference to FIG. 4, there is shown a block diagram of a transmitter unit 400 that includes a digital signal processing circuitry 402, a digital-to-analog converter (DAC) 404, and an optical driver integrated circuit 406. The optical driver integrated circuit 406 includes a variable gain amplifier 408, a pre-driver 410, an amplification chain 412 and a differential amplifier 414. The transmitter unit 400 further includes a modulator 416.

The transmitter unit 400 includes suitable logic, circuitry, and/or interfaces that is configured to have a transmit path comprising the differential amplifier 414. The differential amplifier 414 corresponds to the differential amplifier 100A (of FIG. 1A) and its various alternative implementation forms (i.e. the differential amplifiers 100E, 200, 300). Thus, all the operations executed by the differential amplifier 414 are part of the operations executed by the transmitter unit 400. The transmitter unit 400 may also be referred to as a transmitting device or a transmitter. Examples of the transmitter unit 400 includes, but is not limited to, a broad band monolithic integrated circuit, a broad band driver amplifier, a customized hardware for the high data rate optical communication system, or any other portable or non-portable optical device.

The digital signal processing circuitry 402 includes suitable logic, circuitry, and/or interfaces that is configured for signal processing. The digital signal processing circuitry 402 is used to perform computations on digital signals. Examples of the digital signal processing circuitry 402 includes, but is not limited to, an optical digital signal processor (oDSP), a general-purpose digital signal processor or a specific-purpose digital signal processor. The digital-to-analog converter (DAC) 404 includes suitable logic, circuitry, and/or interfaces that is configured for signal conversion from digital domain to analog domain. The digital-to- analog converter (DAC) 404 further communicates the analog signal to the optical driver integrated circuit 406 for amplification.

The optical driver integrated circuit 406 includes suitable logic, circuitry, and/or interfaces that is configured for providing sufficient signal amplification as required to drive the modulator 416. The optical driver integrated circuit 406 is a broadband or a high bandwidth amplifier which can provide high data rate and high gain as well.

The variable gain amplifier 408 includes suitable logic, circuitry, and/or interfaces that is configured to provide a variable gain to the analog signal.

The pre-driver 410 includes suitable logic, circuitry, and/or interfaces that is configured to act as an amplifier (or a pre-amplifier). The variable gain amplifier 408 and pre-driver 410 collectively make the amplification chain 412 which provides the sufficient amplification on requirement basis.

The differential amplifier 414 includes suitable logic, circuitry, and/or interfaces that is configured as a linear broadband amplifier to follow the amplification chain 412 to achieve a high output voltage swing and to drive the modulator 416. The differential amplifier 414 is connected between the pre-driver 410 and the modulator 416. The differential amplifier 414 corresponds to the differential amplifier 100A (of FIG. 1A) and its various alternative implementation forms (i.e. the differential amplifiers 100E, 200 or 300).

The modulator 416 (e.g. an optical modulator) includes suitable logic, circuitry, and/or interfaces that is configured to modulate a beam of light (e.g. a laser beam). Examples of the modulator 416 includes, but is not limited to an amplitude modulator, phase modulator, polarization modulator, spatial light modulator and many alike.

The transmitter unit 400 provides a high bandwidth and a high amplification gain required for a high data rate wired or optical communication system by use of the differential amplifier 414. For example, the high data-rate optical communication system requires broadband technique in the context of an amplifier design that can precede or follow an equalizer or act as a pre driver in a transmitter front end such as the transmitter unit 400. The requirement of wide bandwidth is fulfilled by the differential amplifier 414 in the transmitter unit 400. The transmitter unit 400 has a high amplification gain that is required to achieve a high linear output voltage swing and to drive the modulator 416 because of the differential amplifier 414. FIG. 5 is a block diagram that illustrates various exemplary components of a receiver unit, in accordance with an embodiment of the present disclosure. FIG. 5 is described in conjunction with elements from FIGs. 1A, 1E, 2 and 3. With reference to FIG. 5, there is shown a block diagram of a receiver unit 500 that includes a first diode 502, a second diode 504 and an optical transimpedance amplifier integrated circuit 506. The optical transimpedance amplifier integrated circuit 506 includes a low noise amplifier 508, a variable gain amplifier 510, an amplification stage 512, and a differential amplifier 514. The low noise amplifier 508 includes a first variable resistor 508A and a second variable resistor 508B.

The receiver unit 500 includes suitable logic, circuitry, and/or interfaces that is configured to have the differential amplifier 514. The differential amplifier 514 corresponds to the differential amplifier 100A (of FIG. 1A) and its various alternative implementation forms (i.e. the differential amplifiers 100E, 200 or 300). Thus, all the operations executed by the differential amplifier 514 are part of the operations executed by the receiver unit 500. The receiver unit 500 may also be referred to as a receiving device. Examples of the receiver unit 500 includes, but is not limited to a broad band monolithic integrated circuit, a broad band transimpedance amplifier (TIA), a customized hardware for the high data rate optical communication system, a receiver, or any other portable or non-portable optical device.

Each of the first diode 502 and the second diode 504 (e.g. a pin photodiode) includes suitable logic, circuitry, and/or interfaces that is configured as a diode which behaves like a resistor without producing any distortion or rectification of a signal. The arrows in the first diode 502 and the second diode 504 represent light or photons.

The optical transimpedance amplifier integrated circuit 506 (optical TIA IC) includes suitable logic, circuitry, and/or interfaces that is configured to have various amplification stages (e.g. the amplification stage 512. The amplification stage 512 includes various amplifiers (e.g. the low noise amplifier 508 and the variable gain amplifier 510) and each of them with high bandwidth in order to avoid the degradation of sensitivity of the receiver unit 500 due to a reduced gain. Moreover, the optical transimpedance amplifier integrated circuit 506 includes a post-amplifier (i.e. the differential amplifier 514) in order to overcome a noise of subsequent parts of the receiver unit 500, if any.

The low noise amplifier 508 includes suitable logic, circuitry, and/or interfaces that is configured to amplify the signal in order to overcome a noise, if any, which may be introduced further by other parts of the receiver unit 500. Each of the first variable resistor 508A and the second variable resistor 508B include suitable logic, circuitry, and/or interfaces that is configured to have variable resistance and based on that amplification of the signal can be varied.

The variable gain amplifier 510 includes suitable logic, circuitry, and/or interfaces that is configured to provide a variable gain to the signal.

The differential amplifier 514 includes suitable logic, circuitry, and/or interfaces that is connected after the low noise amplifier 508 and or the variable gain amplifier 510 preventing to limit the cascaded total bandwidth of the system (the receiver unit 500). The differential amplifier 514 corresponds to the differential amplifier 100A (of FIG. 1A) and its various alternative implementation forms (i.e. the differential amplifiers 100E, 200 or 300).

The receiver unit 500 provides a high bandwidth and high gain required for a high data rate optical communication system by use of the differential amplifier 514. The receiver unit 500 is able to perform in high bandwidth optical communication system without having any sensitivity degradation by virtue of the differential amplifier 514.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including", "comprising", "incorporating", "have", "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration". Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments and/or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments". It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the present disclosure, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.