The present invention generally relates to calibration systems for analog-digital- converters; and more particularly a system and method to correct linearity error related to a split-capacitor digital-to-analog (split-CDAC) devices.

BACKGROUND OF INVENTION

It is a common practice to convert an analog signal into a digital signal to be applicable in various industries. In order to achieve this, analog-to-digital converters (ADCs) play a pivotal role in this process, hence engineers have been developing methods/devices that could increase the accuracy, lowering the power consumption or merely reducing the cost of fabrication. One of the primary challenges is majorly related to the differential nonlinearity error when it comes to ADC. In many cases, the differential nonlinearity error could cause nonmonotonic resulting to missing codes. It is found that this condition may be caused by mismatch and parasitic mismatch in split CDAC architecture. At present there is a great majority of devices, techniques, methods and systems that are developed towards ameliorating the calibration process for ADC so as to increase accuracy. An exemplary of the prior art that attempts to solve issues related to calibration in ADC is a patent issued to Fang-shi et al, US Patent No. US 8,416,105. Although the system discloses integrated circuit of calibration scheme for correcting linearity error of a data acquisition system particularly for a successive approximation analog-to- digital converter (SAR-ADC); the system and method does not teach explicitly the concept of zone tuning.

Thus, there is a need to provide an improved device and system that could address the above problem associated to nonlinearity or linearity error involving the deployment of ADCs. SUMMARY

In one aspect, the present invention provides a system for correcting linearity error of a data acquisition system particularly for a successive approximation analog-to- digital converter the system comprising: a comparator; and a digital calibrator module; characterized in that, the digital calibrator module comprising: a first and second counter adapted to count a number of low “0” from the comparator, in which the counting ceases when the at least one counter reaches a simple majority; a de multiplexer adapted to generate signals based on the comparator’s feedback; a state machine adapted to control a sampling phase, calibration phase and comparison phase; a multiplexer select adapted to control an external multiplexer; a tunable capacitor counter which decrements or increments after the first counter or second counter reaches majority decision and produces signals to reset the first counter and second counter; and; a switch decoder adapted for converting the tunable capacitor counter feedback to match with that of the tunable capacitor.

In a preferred embodiment, once the first counter the majority, then a capacitor value of C _v is reduced by a 1CU, and a lower zone is created. In the preferred embodiment, if the second counter reaches the majority, then the capacitor value of C _v is increased by 1CU, and an upper zone is created.

Preferably, the calibration system is adapted to: calibrate a capacitor unit value to solve capacitor mismatch to resolve the linearity and missing code error; and produce the value of the pattern sampling phase (S) , wherein the final value is used for calibration.

Preferably the system is implemented in digital state machine.

Preferably, the system is further adapted to perform the following: calibrating the capacitor unit value to solve capacitor mismatch to resolve the linearity and missing code error; producing the value of the pattern sampling phase (S) wherein the final value is used for calibration;; controlling the functionalities of the digital calibrator based on the state machine; setting the tunable capacitor to a default value and external multiplexer to select a calibration path; setting the external multiplexer to use an SAR path; and controlling the tunable capacitor and multiplexers select signals such that they are maintained until the system is powered down or reset. Preferably, in tuning the capacitor comprises of Zone Finder Phase Module, the Coarse Tuning Phase Module and the Fine Tuning Phase Module.

Preferably, the Zone Finder Phase Module is adapted to: decrease the capacitor value by one capacitor unit if the first counter reaches the majority, then setting the zone as the lower zone, or increase the capacitor value by one capacitor unit if the second counter reaches the majority, then setting the zone as the upper zone and generate a signal for entering the Coarse Tuning Phase.

Preferably, the Coarse Tuning Phase Module and the Fine Tuning Phase Module of the lower zone are adapted to perform the following tasks: decreasing the capacitor value by one capacitor unit if the first counter reaches the majority in the Coarse Tuning Phase, repeating the calibration for all patterns until second counter wins the majority decision, then increasing the capacitor value and entering the Fine Tuning Phase, repeating the calibration for the entire pattern in Fine Tuning Phase, where whenever the second counter reaches the majority, increasing the fine phase capacitor value, repeating the calibration for all patterns until first counter wins the majority decision. The final tunable capacitor value selected is the last running capacitor value. Preferably, the Coarse Tuning Phase and the Fine Tuning Phase of the upper zone is adapted to: increase the capacitor value by one capacitor unit if the second counter reaches the majority in the Coarse Tuning Phase, repeat the calibration for all patterns until first counter wins the majority decision, then decreasing the capacitor value and entering the Fine Tuning Phase, repeat the calibration for the entire pattern in Fine Tuning Phase, where whenever the first counter reaches the majority, decreasing the fine phase capacitor unit value, repeat the calibration for all patterns until second counter wins the majority decision; wherein the final tunable capacitor value of the third counter selected is the second last running capacitor value that first counter win the majority. Preferably, the system further calibrates a capacitance, wherein the calibration of capacitance comprises of tuneable capacitor and is based on a predefined capacitance value. In a preferred embodiment, a total capacitor’s value is obtained based on the calibration, wherein the total capacitor’s value is controlled by at least one tunable capacitor switches, which is connected to a signal po_cv from the digital calibrator module. BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be more understood by reference to the description below taken in conjunction with the accompanying drawings herein: FIGURE 1A to FIGURE 1C provide an overall block diagram of the system in accordance with a preferred embodiment of the present invention;

FIGURE 2 and FIGURE 3 show the split CDAC using auto-calibration algorithm is implemented in digital state machine and the working mechanism;

FIGURE 4 shows the tuner capacitor module in accordance with a preferred embodiment of the present invention; and

FIGURE 5 shows an example of values with respect to the tuner capacitor module in accordance with a preferred embodiment of the present invention.

DETAILED DESCRIPTION

In line with the above summary, the following description of a number of specific and alternative embodiments is provided to understand the inventive features of the present invention. It shall be apparent to one skilled in the art, however that this invention may be practiced without such specific details. Some of the details may not be described at length so as not to obscure the invention. For ease of reference, common reference numerals will be used throughout the figures when referring to the same or similar features common to the figures. In one aspect, the present invention provides a digital calibration system as well as method to correct linearity error of a split-capacitor digital-to-analog (split-CDAC) data acquisition system. In one embodiment, the system enables the calibration of the nonlinearities of a split-CDAC in successive approximation analog-to-digital converter (SAR-ADC), mainly caused by non-binary weights due to capacitor mismatch and parasitic. The system in accordance with a preferred embodiment, comprising digital state machine algorithm, a split capacitive digital-to-analog converter (split-CDAC) having plurality of bits tunable capacitor for calibration. The invention is further enabled for calibrating total capacitor’s value through controlled switches from the digital calibrator.

FIGURE 1A - FIGURE 1C show the digital calibrator module 50 in accordance with the preferred embodiment of the present invention. The invention may be adapted to implement the calibration algorithm. In one preferred embodiment, the system comprises of de-multiplexer 100, a first counter CNT0 101 , a second counter CNT1 102, state machine 106, multiplexer select 103, a tunable capacitor C _v counter 104 and switch decoder 105.

De-multiplexer 100 is adapted to receive feedback from the comparator, in which when the feedback from the comparator is Low (L), it gives signals High (H) to the first counter CNT0 101. Otherwise, it gives signals H to the second counter CNT1 102. In the preferred embodiment, the first counter ONTO 101 is adapted to count the number of low O', from the comparator. This process is ceased when the CNT1 Counter 102 reaches majority. The second counter CNT1 102 is adapted to count the number of high from the comparator. Similarly, the process is ceased when the first counter ONTO 101 Counter reaches majority.

The multiplexer select 103 in accordance with the preferred embodiment of the present invention is adapted to control an external multiplexer, for instance, SMUX, either data path is from SAR or digital calibrator. The tunable capacitor counter or the third counter in this arrangement, mentioned in the preceding paragraph, Cv Counter 104 is a block counter, also referred to as tunable capacitor counter in which is adapted to be activated or incremented after the second counter CNT 1 102 reaches majority. It produces signals to reset the first counter CNT0 and second counter CNT1 101, 102, respectively. The switch decoder 105 is adapted to convert the tunable capacitor counter C _v 104 result to match with the deployed tuning capacitor or capacitor being tuned. The state machine 106 is adapted to control the sampling phase, calibration phase and comparison phase. Examples of the primary functionalities of the state machine 106 are as shown in FIGURE 2 and FIGURE 3 referred therein as 200, 201. In accordance with the preferred embodiment of the present invention, the state machine controls the functionalities of the digital calibrator 50. The method of digital calibration performed by the state machine 106 in accordance with a preferred embodiment of the present invention will now be described with reference to FIGURE 3. After power up and activated, the tunable capacitor C _v 104 is set to the default value and the external multiplexer is set to select the calibration path. There are three phases of tuning -Zone Finder Phase, Coarse Tuning and Fine Tuning Phase. Initially, it is set to the Zone Finder Phase. The first counter CNT0 101 and second counter CNT1 102 are reset before every calibration.

During the calibration in the Zone Finder Phase, if the first counter CNT0 101 reaches the majority, then the value of third counter C _v is reduced by 1CU. The zone is set as the Lower Zone. Otherwise, if the second counter CNT1 102 reaches the majority, then the value of the tunable capacitor counter C _v 104 is increased by 1CU. The zone is set as the Upper Zone. Upon determination of Lower and Upper zones, the next step is the Coarse Tuning Phase. The processes involved in the Coarse Tuning and the Fine Tuning Phase for each zone are different. The following paragraphs describe the roles of the zones in accordance with the preferred embodiment of the system and method of the present invention.

Firstly, in Lower Zone, during the calibration in the Coarse Tuning Phase, if the first counter CNT0 101 reaches the majority, then the value of the tunable capacitor counter C _v 104 is reduced by 1CU. The processes are repeated for all the patterns until the second CNT1 102 wins the majority decision. Then the value of the tunable capacitor counter C _v 104 is increased by 0.25CU and the process enters the Fine Tuning Phase. During the calibration in the Fine Tuning Phase, repeats all the patterns. If the second counter CNT1 102 reaches the majority, the value of the tunable capacitor counter C _v 104 is increased by 0.25CU. The processes are repeated for all the patterns until first counter CNTO 101 wins the majority decision. The final third counter C _v 104 value is the value that we are looking for and it is used during the SAR process. In the Upper Zone, the process is in opposite to that of the calibration process in the Lower Zone. During the calibration in the Coarse Tuning Phase, if the second counter CNT1 102 reaches the majority, then the value of tunable capacitor counter C _v 104 is increased by 1CU. The processes are repeated for all the patterns until the first counter CNTO 101 wins the majority decision. Then the value of the third counter C _v 104 is reduced by 0.25CU and the process enters the Fine Tuning Phase. Accordingly, during the calibration in the Fine Tuning Phase, repeats all the patterns. If the first counter CNTO 101 reaches the majority, the value of the third counter C _v 104 is reduced by 0.25CU. These processes are repeated for all the patterns until the second counter CNT 1 102 wins the majority decision. The final value of the third counter C _v 104 is the previous value of the third counter C _v 104 in which the first counter CNTO 101 wins the majority. After the final value of the tunable capacitor counter C _v 104 is set, the digital calibrator module 50 sets the external multiplexer to use the SAR path. The tunable capacitor counter C _v 104 and multiplexers select signals are maintained until the system is powered down or reset. If bypass mode is applied, this module will set the tunable capacitor counter C _v 104 as the default value and set calibration phase is complete. The multiplexers are allowed to open the path for SAR block.

The tunable capacitors 202 in accordance with the preferred embodiment of the present invention is shown in FIGURE 4. In this system and method, all capacitor's value is the same. The total capacitor’s value is controlled by the po_cv[0-21], which is connected to the signal from the digital calibrator module 50. The range of this tunable capacitor is 0CU to 20 CU. The example of values is shown in the FIGURE 5, 203. Before calibration, the ADC output produces result at about 10 CU. By starting the calibration at 10.0 CU, the iteration becomes relatively shorter for most cases.

As would be apparent to a person having ordinary skilled in the art, the afore- described methods and components may be provided in many variations, modifications or alternatives calibration systems. The principles and concepts disclosed herein may also be implemented in various manner or form in conjunction with the hardware or firmware of the systems which may not have been specifically described herein but which are to be understood as encompassed within the scope and letter of the following claims.